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At what point is rrdy bit set in nios uart?

Altera_Forum
Honored Contributor II
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Hi, When am receiving a character with the nios uart, it looks like the rrdy bit is being set at some point during reception of the stop bit, instead of at the end of the stop bit. Is that true and if so, at what point within the stop bit time (50%, etc.) is rrdy set? Thanks!

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