I have been creating Avalon Memory Mapped master and slave interfaces for my custom components in my system. I have read through the Avalon specification multiple times, but I find one aspect of it confusing.
In the section "3.5.4 Pipelined Transfers", it specifies that write transfers cannot be pipelined.
However, the specification provides a writeresponsevalid signal which allows the slave to signal when a write response is valid on the response bus. (Which, by the way, writeresponsevalid is listed under the header "Pipeline Signals" in section "3.2 Avalon Memory-Mapped Interface Signal Roles".) The presence of the signal does not specifically imply that write transfers could be pipelined, but it would be possible using this signal in conjunction with the response bus.
The thing that really confuses me is that there is an interface property called pendingWriteTransactions, which is "the maximum number of pending non-posted writes that a slave can accept or a master can issue". So, if a slave was not allowed to pipeline writes, how would the value of this property ever be anything but 1 (or 0, in the case that writeresponsevalid is not implemented)?
