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Avlalon slave Bus

Altera_Forum
Honored Contributor II
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Hello every Body; 

I have made an avalon bus slave component, it have a pipeline structur and it have about 30 clk cycle latency, i made a shift register to get the datavalid signal, and I make the waitrequist signal always equal zero; 

does I made the correct Cochise t for these 2 signals? 

Thanks
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Altera_Forum
Honored Contributor II
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It depends. If your component is still able to process one request per clock cycle, giving data back with the 30 cycle latency, then you are right. But if your component is only able to process one request at a time, requiring 30 cycles, then you shouldn't use the read data valid signal and just stall the master for 30 cycles with the waitrequest signal.

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Altera_Forum
Honored Contributor II
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Thanks Mr Daixiwen for your attention.

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