Bad start-byte

[Altera_Forum]

Hello, 

 I&#39;m trying to get the nios2-flash-programmer to work with a custom board. I have a Microtronix Stratix development board and I&#39;ve been able to create a flash-programming design for this board (SODIMM Flash) using mk_target_board. This seems to work OK and the nios2-flash-programmer has no trouble at all.  However this does not work with my custom board which uses an AMD AM29LV320D Flash device which is CFI compliant. This is a 4Mbyte x 16 chip so I configured the SOPC builder interface to have 21 address bits and 16 data bits. I created a special flash-programming design using mk_target_board and was able to select my custom board as the target hardware through SOPC builder.  Everything seems to work OK except for the nios2-flash-programmer. I compiled and ran the &#39;Flash memory tests&#39; which were included with the Nios II IDE and everything passed OK. Here&#39;s the output from that:  <----> Running Flash Tests <----> This will take approximately 1 minute  -Testing flash info retrieval... This is not the standard reference design Flash name /dev/kernel_flash This flash has 2 erase regions Start 0x 0 End 0x 10000 Number of Blocks 8 Block Size 0x 2000 Start 0x 10000 End 0x 400000 Number of Blocks 63 Block Size 0x 10000  passed. -Testing flash write...  0x10000: ****************************** passed.  0x1ff00: ****************************** passed.  0x10100: ****************************** passed. -Testing flash block erase... passed. -Testing flash block write... passed. -Testing unaligned writes..... passed. All Tests Passed! Exiting Flash Tests   So it looks like the hardware is connected properly and the Nios II is able to access it without any problems.   The problem arises when I try to use the nios2-flash-programmer called from either the Nios II IDE GUI or the Nios II SDK command line. The program calls quartus_pgm to program the .sof file OK; but after this is finished it crashes with the following error message:   [SOPC Builder]$ nios2-flash-programmer --sof=../../../proc_bd_flash/system/proc_bd_flash.sof --cable=ByteBlasterII --device=2  --base=0x00800000 --input=kernel_flash.flash --debug --verbose Nov 2, 2004 9:29:49 AM - (FINE) nios2-flash-programmer: nios2-flash-programmer starting Nov 2, 2004 9:29:49 AM - (INFO) nios2-flash-programmer: args = --sof=../../../proc_bd_flash/system/proc_bd_flash.sof --cable=ByteBlasterII --device=2 --base=0x00800000 --input=kernel_flash.flash --debug --verbose Nov 2, 2004 9:29:49 AM - (INFO) nios2-flash-programmer: Attempting to read input-data from kernel_flash.flash Nov 2, 2004 9:29:49 AM - (INFO) nios2-flash-programmer: Launching Quartus Programmer to download: ../../../proc_bd_flash/system/proc_bd_flash.sof Nov 2, 2004 9:29:49 AM - (FINE) nios2-flash-programmer: Quartus Pgm launched Info: ******************************************************************* Info: Running Quartus II Programmer Info: Command: quartus_pgm --no_banner --mode=jtag --cable="ByteBlasterII" --operation=p;../../../proc_bd_flash/system/proc_bd_flash.sof@2 Info: Using programming cable "ByteBlasterII [LPT1]" Info: Started Programmer operation at Tue Nov 02 09:29:53 2004 Info: Configuring device index 2 Info: Device 2 contains JTAG ID code 0x020030DD Info: Configuration succeeded -- 1 device(s) configured Info: Successfully performed operation(s) Info: Ended Programmer operation at Tue Nov 02 09:30:13 2004 Info: Quartus II Programmer was successful. 0 errors, 0 warnings  Info: Processing ended: Tue Nov 02 09:30:13 2004  Info: Elapsed time: 00:00:20 Nov 2, 2004 9:30:13 AM - (FINE) nios2-flash-programmer: SOF programming done. exit code = 0x0000 Bad start-byte Failed to get header for variable-payload packet. Nov 2, 2004 9:30:16 AM - (SEVERE) nios2-flash-programmer: Error opening target hardware Nov 2, 2004 9:30:16 AM - (SEVERE) nios2-flash-programmer: Unable to open flash-device after successfully communicating with target. It is likely that you are using a flash-programming FPGA design which was not created for your target board.   In order to program flash, you must first create a purpose-built flash-programming design (i.e. FPGA configuration) and associate it with  your particular board. The Nios development kit is delivered with purpose-built flash-programming designs pre-built for several   development boards. If you wish to program flash on your own board, you must first create a flash-programming design.   The process of creating a flash-programming design for your board is mostly automated. From a bash-shell, execute this script:   mk_target_board --help   The help-message includes references to other documentation on programming flash and targeting Nios systems to custom board designs.  - exiting.    I think the key part of the error message is:  -----> Bad start-byte -----> Failed to get header for variable-payload packet. -----> Nov 2, 2004 9:30:16 AM - (SEVERE) nios2-flash-programmer: Error opening target hardware -----> Nov 2, 2004 9:30:16 AM - (SEVERE) nios2-flash-programmer: Unable to open flash-device after successfully communicating with target.  It is likely that you are using a flash-programming FPGA design which was not created for your target board.    Has anybody else encountered this problem or know of a way to work around it?  Thanks, Terry

[Altera_Forum]

Hello Terry, 

 I have had many problems with the flash programmer (which are not solved, but I know why now :-) ) and I think that a possible cause to your problem is the frequency of your design. What speed do you run the FPGA ? I had problems when my design did not run around 50 MHz (40 failed, but 60 too....). In my case the error changed regularly (bad start byte, bad JTAG frame or no communication at all). To solve this I had to add a PLL at the clock input of the FPGA, and a delay on the reset pin of the Nios2 to allow the PLL to stabilize (but not too long because it caused problems too, probably a time out...). I used approximately the same delay as the one used in the default design (from altera) of my cyclone dev board (the cout of an 11-bit counter worked the best for me, when my input clock was 20Mhz and that I tried to boost it up to 50 MHz with a PLL).  I hope this helps  Pod

[Altera_Forum]

Pod, 

 The oscillator into the chip is running at 50 MHz, but maybe I&#39;ll try adding a PLL to the input and see if that helps.  Thanks for the suggestion.  -- Terry