Basic SDRAM/NIOS question

[Altera_Forum]

Hello:  

 I'm new here. Here's a fairly basic question (I think)... an answer to which I have been unable to find.  I have a NIOS2 cyclone development board. What I want to do is read data from SDRAM (14 bits at a time) and clock it into a DAC using the PIO core.   My question is this... Let's say I want to clock these 14 bit values into the DAC at a rate of 5 MHz (the clock would have to be generated from the fpga as well... possibly sysclk divided down). But here's the problem- how do I write these 14 bits to the PIO pins at a fixed rate so as to follow the timing constraints of the DAC chip? Is it a difficult task to do this with SDRAM?   Or should I just do a DMA to SRAM and control that using my own design outside of NIOS.  Thanks in advance.  --

[Altera_Forum]

--- Quote Start ---  originally posted by fpgazz@Apr 14 2005, 01:11 PM hello:    i'm new here.  here's a fairly basic question (i think)... an answer to which i have been unable to find.  i have a nios2 cyclone development board.  what i want to do is read data from sdram (14 bits at a time) and clock it into a dac using the pio core.    my question is this...  let's say i want to clock these 14 bit values into the dac at a rate of 5 mhz (the clock would have to be generated from the fpga as well... possibly sysclk divided down).  but here's the problem- how do i write these 14 bits to the pio pins at a fixed rate so as to follow the timing constraints of the dac chip?  is it a difficult task to do this with sdram?    or should i just do a dma to sram and control that using my own design outside of nios.  thanks in advance.  --  --- Quote End ---   i think you'd better develop a user register slave,the nios only write the dac datas into it,then it can write the datas at 5MHZ to your dac.

[Altera_Forum]

yesdingsheng, 

Seems to me that you need a streaming PIO. Streaming is a seldom-used facet of the Avalon bus, but it fits the bill here. The HDL below implements a write-only streaming register; you can drive it from a DMA. You didn&#39;t say what version of the tools you have. The HDL should be importable from the Component Editor, or from the User Defined Interface with a bit more work. The new component should be defined as an Avalon Register Slave with 0 write wait states. Edit the Verilog parameters to suit your application. Let me know if this works for you.  module streaming_pio (  // inputs:  clk,  reset_n,   write_n,  writedata,   // outputs:  readyfordata,  pio_output  );   parameter DATA_WIDTH = 14;  parameter OUTPUT_RATE_HZ = 5000000;  parameter CLOCK_RATE_HZ = 50000000;  parameter PIO_RESET_VALUE = 0;   // Calculated parameter (not editable in GUI).  parameter RELOAD_VALUE = ((CLOCK_RATE_HZ / OUTPUT_RATE_HZ) - 1);   input clk;  input reset_n;  input write_n;  input [(DATA_WIDTH - 1) : 0] writedata;  output readyfordata;  output [(DATA_WIDTH - 1) : 0] pio_output;   reg [31 : 0] counter;  wire [31 : 0] p1_counter =  (~readyfordata & |counter) ? (counter - 1) :  (~write_n & readyfordata) ? RELOAD_VALUE :  counter;   always @(posedge clk or negedge reset_n) begin  if (~reset_n) begin  counter <= RELOAD_VALUE;  end  else begin  counter <= p1_counter;  end  end    wire readyfordata = ~|counter;   reg [(DATA_WIDTH - 1) : 0] pio_output;  wire [(DATA_WIDTH - 1) : 0] p1_pio_output =  ~write_n & readyfordata ? writedata :  pio_output;    always @(posedge clk or negedge reset_n) begin  if (~reset_n) begin  pio_output <= PIO_RESET_VALUE;  end  else begin  pio_output <= p1_pio_output;  end  end  endmodule

[Altera_Forum]

Sounds like you need to buffer this data (using a FIFO). So contents are read out at 5MHz, and data is written into it at something considerably higher. Using signals that tell you whether the buffer is full (or close to getting full) you can have the master back off from writing into it. This is common practice in DSP type applications where you have to keep data rates constant.

[Altera_Forum]

BadOmen, 

You&#39;re right, a FIFO is required to ensure that data is always available to be written to the DAC at the right instants. My suggestion is to import the HDL I posted as a streaming Avalon slave, and master that slave with the Avalon DMA. In that system, the DMA&#39;s internal FIFO provides the necessary buffering. Depending on various other aspects of your system, it may be necessary to configure the DMA to have a larger FIFO than its default - you&#39;ll know you need to do that if the DMA write master isn&#39;t able to write to the PIO at the required rates due to an empty FIFO condition (this is easy to observe in ModelSim).  fpgazz, let me know if this suggestion makes sense to you.

[Altera_Forum]

Kero Kero Keroppi: 

 Thanks. And thanks to everyone else who responded. I will try what you suggest and post my findings and further questions here.  Regards, fpgazz

[Altera_Forum]

fpgazz, 

I created a simple Avalon peripheral, streaming_output_register, which provides the function you need. Check it out in the "Post your own IP" section.

[Altera_Forum]

Too cool.. thanks. I will check this out and send you some feedback.