Bootloader problems

Altera_Forum · ‎11-29-2006

Hello guys,

We have made our own bootloader, which boots a cyclone 1 and a stratix GX.

First the Cyclone configures himself through an EPCS. The configuration which is loaded in the Cyclone loads another configuration, from a flash device, with a small bootloader program in the onchip-memory into the Stratix GX. When this is done the bootloader request the Nios-code for the actual program from the cyclone. The Cyclone then transfers the Nios-code to the Stratix GX's SRAM.

after this the bootloader wil be stopped and there is a jump in the bootloader code to the address of the first word in the sram where the nios-code is stored.

so far everything goes fine..... but when the code jumps to the Sram. My nios program won't run... what could be the problem?

I know that SRAM is filled with the correct data because in the debug mode I can see it getting filled and that data is the same as the data provided by my script.

I know that my jump works because when I let the bootloader code jump to the SRAM I can see that the bootloader start over and over again.

this is my bootloader code:

I did compile my bootloader program with the reset addres to onchip_memory and the exception_addres to SRAM in SOPC

When i compiled my test program, the one that stands in SRAM, I compiled it with both the exception and reset addres at SRAM.

Hope you guys have some tips for me....

Thanks in advance

Altera_Forum · ‎11-30-2006

Problem solved!!!

I did everything the right way... but SOPC-builder was my problem.. Somehow sopc-builder doesn't save data when you hit the "exit-cross" in the upper right corner. It only saves when you hit the exit button!

so every change i made around the reset and exception addresses had no effect!!

maybe Altera could include an Save button in SOPC-builder.. this would clearify this sort of problems in my line of view...

Altera_Forum · ‎01-17-2007

Hi,

I'm working on a system that I think is quite similar to the one you describe above.

My hw is so configured:

- NiosII

- OnChipMemory

- SDRAM controller

- PCI Compiler

- other peripherals

Nios CPU has reset address in OnChipMemory, exception address is in external SDRAM.

My goal is boot Nios in OnChipMemory, wait for firmware is loaded into SDRAM from an external PCI master and the jump with program execution in SDRAM.

I already wrote both loader and firmware, and I have them running in two different Nios IDE projects, the first is configured (Sys Lib Options) to reside in OnChipMemory, the other in SDRAM.

My doubt is about how to get from IDE the binary file to be copied in SDRAM (the firmware binary image) and choosing the right address to jump in.

Binary Image: I've tried with

nios2-elf-objcopy -O binary

but addresses in the file I obtain is not aligned as I can see from debugger, what I see in file is in memory starting from 0x20.

Jump: I jump to _start section, is it right? I also have to setup stack pointer or not? Starting from that point is all the C setup code correctly executed in you opinion?

One more question, I can't see your's bios code in the post above, did you remove it for privacy issues?

Thanks in advance,

Paolo