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C2H Request !

Altera_Forum
Honored Contributor II
1,628 Views

Hello mates 

I managed to develop my C code using nios II (Quartus 13.0 web edition), as far as I know I should accelerate the functions using HDL.  

I thought there is a tool C2H compiler for Altera environment but I read that it has been abandoned and no longer used !!  

If it is true How I can do the acceleration task ?! 

If not how can I Start it !? Is there any version still support the C2H ?:confused: 

Thnx for advance
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Altera_Forum
Honored Contributor II
691 Views

By far the easiest way is to install the exact tools being used in the tutorial you are following. The c2h users guide cites 9.1

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Altera_Forum
Honored Contributor II
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The whole C to hardware idea doesn't really work. You end up with much more FPGA resource being used than would have been the case if it had been implemented using proper techniques in a hardware description language (HDL) such as Verilog, System Verilog or VHDL. 

 

The Altera C2H compiler was an extra cost add on product that wasn't available in the free Quartus editions. The modern version is Altera SDK for OpenCL. I think it automates more than the old C2H compiler did, but I'm not sure because I haven't used them.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

The Altera C2H compiler was an extra cost add on product that wasn't available in the free Quartus editions.  

 

--- Quote End ---  

 

 

I don't have any web editions installed, but between at least 11.1 and 12.1sp1 no additional license is required to run the C2H tool flows. It was removed in 13. 

 

i.e. if you've got .../nios2eds/components/altera_avalon_c_hardware_accelerator/c2h-generate/c2h-generate there, it will run for you without any additional license, and the generated HDL is clear text.
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Altera_Forum
Honored Contributor II
691 Views

 

--- Quote Start ---  

The whole C to hardware idea doesn't really work. You end up with much more FPGA resource being used than would have been the case if it had been implemented using proper techniques in a hardware description language (HDL) such as Verilog, System Verilog or VHDL. 

 

The Altera C2H compiler was an extra cost add on product that wasn't available in the free Quartus editions. The modern version is Altera SDK for OpenCL. I think it automates more than the old C2H compiler did, but I'm not sure because I haven't used them. 

--- Quote End ---  

 

 

C2H is a bit different from openCL. Open CL requires a CPU controller for the system, C2H is a replacement for HDL. Xilinx do a fairly good job with C to HDL, if you write the C correctly. It is also great for rapid prototyping. 

While I agree HDL should always give the optimum solution. OpenCL and C2H opens the markets much wider to software programmers and gives existing hardware designers the ability to create a firmware based solution very quickly, which may not be optimal, but at least it is something that will work and may be good enough for some.
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Altera_Forum
Honored Contributor II
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So in my case I am on 13.0 web edition without ./nios2eds/components/altera_avalon_c_hardware_accelerator/c2h-generate/c2h-generate 

what to do ? Should I go for C2H manually ?!!
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Altera_Forum
Honored Contributor II
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That is certainly one option, one that has been used since the beginning of FPGAs. Designers would create a model in C and then create the HDL design and compare results from both to see if they matched.

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Altera_Forum
Honored Contributor II
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Another option would be to install older Quartus, in parallel with your existing install, so you can evaluate the tool and see if it is going to help you the way you hoped it would. If you are satisfied, taking the results forward into 13.0 is no problem as the output files are clear text.

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Altera_Forum
Honored Contributor II
691 Views

 

--- Quote Start ---  

Another option would be to install older Quartus, in parallel with your existing install, so you can evaluate the tool and see if it is going to help you the way you hoped it would. If you are satisfied, taking the results forward into 13.0 is no problem as the output files are clear text. 

--- Quote End ---  

 

Much appreciated ! thnx
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