CPU hangs after SDRAM refresh

Altera_Forum · ‎01-29-2005

My design is build with Quartus 4.2-SP1 / NIOS2 1.1 and consists of several peripherals sharing avalon signals. One of them is the 'new sdram controller' with shared signals, the other is an interface to user logic and is connected to an array of DSPs. This peripheral has 8-bit data and is accessed with 16-bit using dynamic bus sizing (which results on avalon side in always reading four bytes but only two of them enabled).

Sometimes my CPU hangs after accessing this device. With SignalTap I've figured out, that this behaviour occurs if the SDRAM refresh starts while the CPU is accessing this peripheral port. An internal node of SDRAM-Controller shows this event (CPU:inst|SDRAM:the_SDRAM|refresh_request). This link shows both: the signals when access is successful and if it fails:

... signal tap results ... (http://www.ing-buero-ruettger.de/nios/error.htm)

I've generated this 8-bit peripheral in two versions: first as 'Interface to user logic' and then as 'Create New Component'. Both types showed the same behaviour.

In SOPC-builder (V4.2 build 178) this SDRAM-Controller reports: 'Latency-aware SDR SDRAM Controller - Version 2.3'. I'm wondering that this component is labeled 'SDRAM_test_component' in the final CPU-symbol.

Do I have the most actual version?

Has anybody an explanation, a workaround, or better a solution?

Mike

Altera_Forum · ‎01-31-2005

Hi Mike,

If you are sure your Quartus version is a final release, not a beta (this 4.2sp1 must be very new, I'm still in process updating to the original v4.2 release) then probably it's a component version conflict problem. Try removing all Altera software (including manually deleting the folders left after uninstall) then install again. Probably it's also worth asking Altera if this new Quartus version is compatible with the Nios release you have, or you need to wait for a new NiosII version as well.

Regards,

C

Altera_Forum · ‎01-31-2005

Hi Mike,

I have tried to figure out your screen-shots, but I am not sure if I understood your design right. If I am correct you have implemented your own avalon-master (the "DSP"). I have used to SDRAM-controller successfully with NIOS-designs and had no problems (at least not of this kind ;-). So maybe you should recheck your own avalon-master interface. (I have never implemented one, so I do not know if there are any pit falls...).

Of course it is also possible that there is a bug in the SDRAM-controller / avalon-switch-fabric that occurs only in your special case.

Regards,

Thomas

P.S.: Nach dem Motto: "Ein Ing.-Buero hilft dem anderen :-)"

Altera_Forum · ‎02-01-2005

clancy,

I have to correct my statement: My design was created with Quartus 4.1, then updated to Quartus 4.2. At this time I've added this 8-bit peripheral and detected this malfunction. But installing the new SP1 didn't solve the problem.

thomas,

no, 'DSP' isn't an avalon master , it is one of several slave periherals all sharing avalon bus signals as it is done by the SDRAM controller. One special property of 'DSP' is, that it is an memory-type peripheral, using dynamic bus sizing. This is done to access TI-DSPs over their HPI-8 interface in order to read their internal 16-Bit data.

In the meantime Altera is looking for a solution. Results are posted soon.

Thanks for your help.

Mike

Altera_Forum · ‎02-01-2005

All,

Today I've got a special patch from Altera that solved my problem. An offical patch for general release will be published by Altera soon.

Mike

Altera_Forum · ‎02-02-2005

Mike,

I believe I'm seeing the same behavior since I upgraded to

Quartus 4.2/Nios-II 1.1.

> Today I've got a special patch from Altera that solved my problem.

In desperation, I'm reverting to Nios-II 1.0, but I'm not sure if that

will matter :-( ... do you know what was actually patched? Quartus,

Nios-II, SOPCBuilder?

BTW: I was told that the Nios-II 1.1 was about to be shipped (this week)

but was pulled at the last minute ... I'm not sure if this was reliable info.

Regards,

--Scott

Altera_Forum · ‎02-02-2005

Scott,

The problem is in Quartus (SOPC Builder), not Nios, so reverting to Nios 2 1.0 won't help. I believe the problem has existed since Quartus II 4.2. I'll email you the same patch I sent to Mike.

Altera_Forum · ‎02-02-2005

> so reverting to Nios 2 1.0 won't help.

Agreed -- I just confirmed this the old-fashioned way ;-)

> I'll email you the same patch I sent to Mike.

That would be great -- thanks for your help!

Regards,

--Scott

Altera_Forum · ‎05-10-2005

All,

Is it possible that I may get a hold of this patch? I have been pulling my hair out with the same problem for the last two weeks. I have been attempting to pull down the Quartus 5.0 Web edition from the ftp site, but it is too slow to download. I need to verify my design but like you guys, the CPU hangs up after the first SDRAM refresh cycle. Iwould appreciate any assistance.

Thanks,

Chris Gamboni

Altera_Forum · ‎05-16-2005

I received Quartus and Nios 5.0 from my local FAE and that solved the problem.

Thanks Mike for the response, I appreciate it.

Chris

Altera_Forum · ‎05-17-2005

Hello all,

I've got the same problem and although the new version of Quartus seems to solve the problem, for the moment I would like to continue working with Quartus 4.2. So could you send me the patch please?. I'll be very thankfull.

Thank you, Luis