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the scheme is : on Stratix IV EP4SGX230
{Processor1 Processor 2} |/ _________ \| {ddr2SDRAM1 ddr2SDRAM2 } operations: 1,time1 ,Processor 1 ACESS SDRAM1,Processor 2 ACESS ddr2SDRAM2 2,time2 ,Processor 1 ACESS SDRAM2,Processor 2 ACESS ddr2SDRAM1 and so on .... can this be implemented? and how ? is there any docs to refer? thanks for your help!Link Copied
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The Avalon bus arbiters will allow both cpu (and any other Avalon masters) to access the memory - so there is not physical problem.
Logically you need to setup the software address maps so that the two processors aren't trying to use the same part of the memory.
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