Can't Access Flash Content with Nios2

[anonimcs]

Hi guys,

I need to use the Nios2 core for one of my designs which I need to use the Nios core for communicating with the "Generic Quad SPI controller II Intel FPGA IP", so that the IP will communicate with the external flash memory we use "MT25QL512ABA". The design is implemented on MAX10 and I'm using Quartus 21.1 Lite edition on Ubuntu 20.04.

To keep things simple, I have created a Nios 2 application & BSP from template, and modified Hello World template for that. I first tried writing data to the flash and then read it back, which works fine. But then I commented out the write function only and then I read irrelevant data (all 1's) and it's not how a flash memory should work (at the end it should not matter if I comment out write function or even reprogram the FPGA after a reboot, the Flash should not lose its data unless the memory blocks are erased). So I think there's something I'm doing wrong/missing. The C code I wrote is given below.

As it can be seen in the code (the commented parts in the for loops) that I tried the functions from both "alt_flash" and "altera_generic_quad_spi_controller2" libraries (both are generated code) as well as direct IO functions with providing the Base offset given in the system.h in the BSP. My code compiles successfully but it seems like it's not even storing my data. I can easily lose the data after a re-compilation without rebooting/reprogramming.

I'd appreciate any help.

Cheers,

int main()
{
        alt_flash_fd                *fd;
	flash_region                *regions;
	int                         numRegions = 0;
        
        int                         ChipNr = 13;
	int                         PatchNr = 7;
	int                         FlashAddr = 0;
	int                         FlashAddrW = 0;
	alt_u32                     readdata = 0;
	alt_u32                     writedata = 0xDEADBEEF;
	alt_u32                     PatchHex = 0x00000000;
	alt_u32                     PhaseHex = 0x0000000A;
	alt_u32                     GainHex = 0x00000020;
	alt_u32                     ChipHex = 0x00000000;
	error_t                     error = 0;
        int                         quad_spi_error = -1;
	alt_u32                     memory_content[112]; // 8 patches * 14 chips

        /* Open the flash device. */
	fd = alt_flash_open_dev(GENERIC_QUAD_SPI_CONTROLLER2_0_AVL_MEM_NAME);
	// for now, only for beam = 0 & block = 0
	PhaseHex = PhaseHex << 8;
	GainHex = GainHex << 1;
	for (int ChipIdx = 0; ChipIdx <= ChipNr; ChipIdx++)
	{
		RowHex = RowHex << 28;
		ColumnHex = ColumnHex << 24;
		for (int PatchIdx = 0; PatchIdx <= PatchNr; PatchIdx++)
		{
			// FlashAddr = PatchIdx * 4 + ChipIdx * 32 + BlockIdx * 512 + BeamIdx * 4096;
			FlashAddr = PatchIdx * 4 + ChipIdx * 32;
			PatchHex = (alt_32)PatchIdx;
			PatchHex = PatchHex << 14;
			ChipHex = (alt_32)ChipIdx;
			ChipHex = ChipHex << 17;
			writedata = RowHex | ColumnHex | ChipHex | PatchHex | PhaseHex | GainHex;
			// IOWR_32DIRECT(GENERIC_QUAD_SPI_CONTROLLER2_0_AVL_MEM_BASE ,FlashAddr, writedata);
			memory_content[PatchIdx + ChipIdx * 8] = writedata;
			printf("initialize_flash_sectors - Writing the data in the flash for patch %x and for chip %d into the address %x. Written data is %x \n", PatchIdx, ChipIdx, FlashAddr, writedata);
		}
	}
// alt_write_flash(fd, FlashAddr, memory_content, 3484);
	quad_spi_error = alt_qspi_controller2_write(fd, 10000 + FlashAddr, memory_content, 3484);
	FlashAddrW = FlashAddr;
	// read in reverse order
	for (int ChipIdx = ChipNr; ChipIdx >= 0; ChipIdx--)
	{
		for (int PatchIdx = PatchNr; PatchIdx >= 0; PatchIdx--)
		{
			// FlashAddr = PatchIdx * 4 + ChipIdx * 32 + BlockIdx * 512 + BeamIdx * 4096;
			FlashAddr = PatchIdx * 4 + ChipIdx * 32;
			// readdata = IORD_32DIRECT(GENERIC_QUAD_SPI_CONTROLLER2_0_AVL_MEM_BASE ,FlashAddr);
			// alt_read_flash(fd, FlashAddr + FlashAddrW, &readdata, 4);
			quad_spi_error = alt_qspi_controller2_read(fd, (alt_u16)(10000 + FlashAddr + FlashAddrW), &readdata, 4);
			printf("initialize_flash_sectors - Reading the data from the flash for patch %x and for chip %d from the address %x. read-back data is %x \n", PatchIdx, ChipIdx, FlashAddr + FlashAddrW, readdata);
		}
	}
        alt_flash_close_dev(fd);

	fd = alt_flash_open_dev(GENERIC_QUAD_SPI_CONTROLLER2_0_AVL_MEM_NAME);

        alt_read_flash(fd, 10448, &readdata, 4);
	printf("initialize_flash_sectors - Testing what is read with altera read flash func from offset Addr 10448. read-back data is %x \n", readdata);

        alt_flash_close_dev(fd);
	return 0;
}

[EBERLAZARE_I_Intel]

Hi,

Can you share your design? I would like to take a look at your qsys design.

[EBERLAZARE_I_Intel]

Hi,

Do you have any update?

[anonimcs · Accepted solution]

Hi,

I have connected the debug reset of Nios2 to the reset port of the QSPI IP (done in the Platform Designer), and connected the QSPI reset of the flash memory with the inverted reset of Nios (QSPI_RST <= nios_reset_n;) in the top level. I can now open the flash device and store/read stuff.

[EBERLAZARE_I_Intel]

Hi,

I’m glad that you are able to solve your issue, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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