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Clock issue with simple DDR4 implementation for Arria 10 SoC Dev Kit

Altera_Forum
Honored Contributor II
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I am using Quartus Prime Version 17.0.0 with the altera arria 10 soc development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html). 

I generated a simple project with an External Memory Interfaces (see picture below) using the Development Kit preset values. 

The goal is to bring the EMIF Avalon MM slave directly to the fabric so that I can test the performance. 

https://alteraforum.com/forum/attachment.php?attachmentid=13774&stc=1  

 

https://alteraforum.com/forum/attachment.php?attachmentid=13775&stc=1  

 

 

Once I generate the HDL for the QSYS, I get the following hierarchy for the EMIF. 

https://alteraforum.com/forum/attachment.php?attachmentid=13776&stc=1  

 

 

As you can see, QSYS generates mem_ck and mem_ck_n which are used as the clock input for the DDR4 modules. 

When I bring those two signals to the top-level IO module and analyze/synthesize the code, Pin Planner adds two more signals to that clock! See image below: 

https://alteraforum.com/forum/attachment.php?attachmentid=13777&stc=1  

 

 

For some reason, Pin Planner believes I need two differential signals for that clock. Do you know what I am doing wrong? 

I am sending you the project on another email in a bit.
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Altera_Forum
Honored Contributor II
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I decided to give a try with the Pro version and the issue vanished, only one differential clock for the DDR4 was generated. 

I repeated it on the Standard Edition and the issue reappeared.
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