Nios® V/II Embedded Design Suite (EDS)
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Contents of EPCS

Altera_Forum
Honored Contributor II
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In order to make a complete EPCS4-update by a running NIOS II system itself, I need to know how the content of the EPCS is build. 

I've figured out: 

- the first part is FPGA configuration with bit swapped data (MSB <-> LSB) as created by sof2flash-utility 

- immediately behind follows my firmware as created by elf2flash-utility 

 

When I use &#39;Flash-Programmer&#39; some more data are programmed behind these two blocks. 

- What else do I need to get an image-file of the EPCS-device ? 

- where is the bootloader (boot_loader_epcs.srec) to be placed to ? 

 

Mike
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Altera_Forum
Honored Contributor II
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In an EPCS you need to store the following data into the device: 

 

- At address 0, the bitswapped FPGA configuration. 

- Immediately after the FPGA configuration, data blocks for the bootloader (see the bootloader sources for details of their format. 

 

You can use elf2flash to generate the data blocks from an elf file.
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Altera_Forum
Honored Contributor II
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The boot-loader .srec is not put into the EPCS flash; it resides in the EPCS controller *inside* the FPGA. This controller has a small on-chip memory that contains the simple boot-loader code; and is used when you point the CPU reset vector to the EPCS controller. 

 

As wombat points out, the only two things that our flash programmer would normally put into the EPCS device itself are FPGA configuration and/or your software flash image.
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Altera_Forum
Honored Contributor II
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Thanks wombat & Jesse, 

 

now I&#39;ve got it running. I was a little bit confused about additional data behind the firmware. But this was obviously buffer junk resulted from previous data blocks during programming. 

 

I&#39;ve written a short ANCII-C programme who concatenates these two parts and makes the bit swapping (MS Visual C). If somebody is interested in, mail me (added later: and send me your eMail address). 

 

Mike
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