Custom instruction decode and D stage pipeline stall

[Altera_Forum]

Does anyone know if the /f pipeline D stage stall (waiting for 'late' result) applies to custom instructions that have the 'readra' or 'readrb' bits deasserted ? 

 AFAICT the decode stage is responsible for fetching the two 32bit values from the register file that correspond to the 'A' and 'B' fields of the instruction, and managing the stall if the required value isn't available yet.  Ignoring 'call' and 'jmpi' (for which there is probably special decode) all instructions require the 'A' field be read. Whether 'B' is needed depends on the opcode, but, in fact, only the lowest 2 bits need be considered (0|3 => write, 1|2 => read) [1][2].  The 'custom' instruction is then likely to be decoded assuming that both the 'A' and 'B' fields refer to registers that need reading. I suspect it is unlikely that the decode unit looks at the readra/readrb bits when making its decisions. This may lead to unexpected (undocumented) pipeline stalls during custom instructions.  The custom instruction logic will use 'writerc' to determine whether to write back the resultant value to the register file.  Another thing that the documentation seems to miss is that since the A/B/C fields are made available to the custom logic, these can be used to control the generated result. In particular the 'B' field can be used to select between various modifications of the 'A' value - eg between 32 and 16 bit byte swaps and 32, 16 and 8 bit bit swaps in a single instruction.  [1] I'm surprised it isn't a single bit. [2] initda/initd/flushda/flushd seem to be encoded in a manner where they might write to 'r0'.