Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12745 Discussions

Cyclone NIOS eval example standard.sof at 25MHz?

Altera_Forum
Honored Contributor II
1,186 Views

Can someone explain what I have to do to run the standard.sof example from the Cyclone NIOS eval board at 25MHz? I thought it would be as simple as changing the PLL from 1/1 to 1/2 but that doesn't seem to work.  

 

Specific questions: 

 

1) Can I simply clock down the SDRAM to 25MHz? 

2) What about the phase shift of -63 in the SDRAM PLL, does it have to change to a different angle at 25MHz? 

3) What about the "connector.pll"? I changed it to 25MHz as well but it seems like it wouldn't affect anything 

4) The "sysclock" (c0 output) of the connector_pll seems to be unused. Is it needed for anything? 

 

Thanks, 

Andrew
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
422 Views

 

--- Quote Start ---  

originally posted by queisser+nov 2 2005, 11:06 am--><div class='quotetop'>quote (queisser @ nov 2 2005, 11:06 am)</div> 

--- quote start ---  

1) can i simply clock down the sdram to 25mhz?[/b] 

--- quote end ---  

 

maybe. it&#39;s already clocked down, and i&#39;m pretty sure that sdram is not static logic. you could just remove the sdram from your system...? 

 

 

--- quote start ---  

originally posted by queisser@nov 2 2005, 11:06 am 

2) what about the phase shift of -63 in the sdram pll, does it have to change to a different angle at 25mhz? 

--- quote end ---  

 

that will probably need tweaking. it&#39;s not used as a phase shift as much as a time delay, so if you halve the frequency, you&#39;ll probably have to halve the phase shift, too, to keep the same time delay. 

 

<!--quotebegin-queisser@Nov 2 2005, 11:06 AM 

3) what about the "connector.pll"? i changed it to 25mhz as well but it seems like it wouldn&#39;t affect anything 

--- Quote End ---  

 

PLLs don&#39;t really use "MHz" as their settings, they use clock multiplier and divider factors... so are you saying you changed it to a 1/2? 

Have you tried getting a 25 MHz oscillator and dropping it in? 

 

As a side note, I remember seeing notes that things like the flash programmer didn&#39;t work below 50 MHz. 

 

 

--- Quote Start ---  

originally posted by queisser@Nov 2 2005, 11:06 AM 

4) the "sysclock" (c0 output) of the connector_pll seems to be unused. is it needed for anything? 

--- Quote End ---  

 

I think it used to be used for the debugger port back in Nios I. If you don&#39;t hook it up, it gets optimized away.
0 Kudos
Altera_Forum
Honored Contributor II
422 Views

 

--- Quote Start ---  

originally posted by queisser+nov 2 2005, 11:06 am--><div class='quotetop'>quote (queisser @ nov 2 2005, 11:06 am)</div> 

--- quote start ---  

1) can i simply clock down the sdram to 25mhz?[/b] 

--- quote end ---  

 

yes, you will see a clk to the external sdram, which comes from e0 of sdram_pll.  

you will have to match the sdram controller clk to 25mhz too.  

 

<!--quotebegin-queisser@Nov 2 2005, 11:06 AM 

2) what about the phase shift of -63 in the sdram pll, does it have to change to a different angle at 25mhz? 

--- Quote End ---  

 

The phase shift needs to be specific in absolute time. Get the phase shift time in "ns" for the 50MHz design, which should be "-4.8ns" if i remember correctly, and set that for the new 25MHz clock.  

 

 

--- Quote Start ---  

originally posted by queisser@Nov 2 2005, 11:06 AM 

3) what about the "connector.pll"? i changed it to 25mhz as well but it seems like it wouldn&#39;t affect anything 

--- Quote End ---  

 

The cyclone device has some hardware specific connections which needs to be there, and the connector pll is one of them.  

 

 

--- Quote Start ---  

originally posted by queisser@Nov 2 2005, 11:06 AM 

4) the "sysclock" (c0 output) of the connector_pll seems to be unused. is it needed for anything? 

--- Quote End ---  

 

Check the pin assignments editor, if it is not connected to anything, then it probably is unused.  

 

 

Btw, my designs have shown that the JTAG_UART needs to be at 50MHz for the nios2-terminal to work correctly. Anyone can get it working at other frequencies?
0 Kudos
Altera_Forum
Honored Contributor II
422 Views

Thanks guys, I played around with it some more and found that halving the phase shift on the SDRAM makes it work. That meshes with the idea of taking the absolute time and converting it back to 25MHz phase angle. 

 

Other than that everything seems to be fine although I didn&#39;t use the nios-terminal.
0 Kudos
Reply