Cyclone V SE Preloader & u-boot

[Altera_Forum]

Hi, 

 I'm trying to bring up a Cyclone V (5CSEBA2U19C8) on a custom board. The problem is, that i can't boot the u-boot.img. Here's my output:   U-Boot SPL 2013.01.01 (Jul 08 2016 - 17:26:30) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 20000 KHz CLOCK: EOSC2 clock 20000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 600 MHz CLOCK: DDR clock 300 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 5000 KHz CLOCK: QSPI clock 2343 KHz RESET: WARM INFO : Watchdog enabled SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 256 MiB ALTERA DWMMC: 0 reading u-boot.img reading u-boot.img Bad image with mismatched CRC # ## ERROR# ## Please RESET the board# ##   I followed the GRSD for Quartus 14.1, my tools are - Quartus 14.1 Build 186 - QSys 14.1 Build 186 - BSP Editor Build 186  The memory device is a Micron mt41j128m16jt-125 (http://192.168.1.106/part-db/show_part_info.php?pid=62) which is available in the HPS configurator (I used this configuration)  I also made a simple DDR3 test which looks like this:  # define CONFIG_SYS_DRAM_TEST # if defined(CONFIG_SYS_DRAM_TEST) # define CONFIG_SYS_MEMTEST_START 0x01000000 # define CONFIG_SYS_MEMTEST_END 0x02000000 int testdram (void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf ("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaa; for (p = pstart; p < pend; p++) { if (*p != 0xaaaa) { printf ("SDRAM test fails at: %08x\n", (uint) p); return 1; } } printf ("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x5555; for (p = pstart; p < pend; p++) { if (*p != 0x5555) { printf ("SDRAM test fails at: %08x\n", (uint) p); return 1; } } printf ("SDRAM test passed.\n"); return 0; } # endif    The test returend no errors. I also tried different u-boot.img files (prebuilts from SoCrates Eval Board and also from SoCKit). Of course I also build my own, which all had the same result.  Disabling the Checksum-Flag in the bsp-editor also had no effect.    Any ideas? It seems nobody else is having this problem. Am I missing something?

[Altera_Forum]

If it helps, i compiled the preloader with debug output. Here's the output: 

  U-Boot SPL 2013.01.01 (Jul 11 2016 - 10:46:04) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 20000 KHz CLOCK: EOSC2 clock 20000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 600 MHz CLOCK: DDR clock 300 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 5000 KHz CLOCK: QSPI clock 2343 KHz RESET: WARM INFO : Watchdog enabled SDRAM: Initializing MMR registers Configuring CTRLCFG Write - Address 0xffc25000 Data 0x000a8042 Read and verify...correct! Configuring DRAMTIMING1 Write - Address 0xffc25004 Data 0x3138ce06 Read and verify...correct! Configuring DRAMTIMING2 Write - Address 0xffc25008 Data 0x0aaaa925 Read and verify...correct! Configuring DRAMTIMING3 Write - Address 0xffc2500c Data 0x00221eb3 Read and verify...correct! Configuring DRAMTIMING4 Write - Address 0xffc25010 Data 0x00000e00 Read and verify...correct! Configuring LOWPWRTIMING Write - Address 0xffc25014 Data 0x00080000 Read and verify...correct! Configuring DRAMADDRW workaround rows - memsize 4294967296 workaround rows - cs 1 workaround rows - width 8 workaround rows - rows 14 workaround rows - banks 3 workaround rows - cols 10 rows workaround - term1 4294967296 rows workaround - term2 524288 rows workaround - bits 1 rows workaround - ilog2 19, 524288 Write - Address 0xffc2502c Data 0x00000e6a Read and verify...correct! Configuring DRAMIFWIDTH Write - Address 0xffc25030 Data 0x00000010 Read and verify...correct! Configuring DRAMDEVWIDTH Write - Address 0xffc25034 Data 0x00000008 Read and verify...correct! Configuring LOWPWREQ Write - Address 0xffc25054 Data 0x00000030 Read and verify...correct! Configuring DRAMINTR Write - Address 0xffc2503c Data 0x00000000 Read and verify...correct! Configuring STATICCFG Write - Address 0xffc2505c Data 0x00000002 Read and verify...correct! Configuring CTRLWIDTH Write - Address 0xffc25060 Data 0x00000001 Read and verify...correct! Configuring PORTCFG Write - Address 0xffc2507c Data 0x0000003f Read and verify...correct! Configuring FIFOCFG Write - Address 0xffc25088 Data 0x00000000 Read and verify...correct! Configuring MPPRIORITY Write - Address 0xffc250ac Data 0x3ffd1088 Read and verify...correct! Configuring MPWEIGHT_MPWEIGHT_0 Write - Address 0xffc250b0 Data 0x21084210 Read and verify...correct! Configuring MPWEIGHT_MPWEIGHT_1 Write - Address 0xffc250b4 Data 0x8081ef84 Read and verify...correct! Configuring MPWEIGHT_MPWEIGHT_2 Write - Address 0xffc250b8 Data 0x00000000 Read and verify...correct! Configuring MPWEIGHT_MPWEIGHT_3 Write - Address 0xffc250bc Data 0x0000f800 Read and verify...correct! Configuring MPPACING_MPPACING_0 Write - Address 0xffc250c0 Data 0x20820820 Read and verify...correct! Configuring MPPACING_MPPACING_1 Write - Address 0xffc250c4 Data 0x08208208 Read and verify...correct! Configuring MPPACING_MPPACING_2 Write - Address 0xffc250c8 Data 0x41041041 Read and verify...correct! Configuring MPPACING_MPPACING_3 Write - Address 0xffc250cc Data 0x00410410 Read and verify...correct! Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0 Write - Address 0xffc250d0 Data 0x01010101 Read and verify...correct! Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_1 Write - Address 0xffc250d4 Data 0x01010101 Read and verify...correct! Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_2 Write - Address 0xffc250d8 Data 0x00000101 Read and verify...correct! Configuring PHYCTRL_PHYCTRL_0 Write - Address 0xffc25150 Data 0x00000200 Read and verify...correct! Configuring CPORTWIDTH Write - Address 0xffc25064 Data 0x00044555 Read value without verify 0x00044fff Configuring CPORTWMAP Write - Address 0xffc25068 Data 0x2c011000 Read value without verify 0x2c03ffff Configuring CPORTRMAP Write - Address 0xffc2506c Data 0x00b00088 Read value without verify 0x00b3ffff Configuring RFIFOCMAP Write - Address 0xffc25070 Data 0x00760210 Read value without verify 0x0076ffff Configuring WFIFOCMAP Write - Address 0xffc25074 Data 0x00980543 Read value without verify 0x0098ffff Configuring CPORTRDWR Write - Address 0xffc25078 Data 0x0005a56a Read value without verify 0x0005afff Configuring DRAMODT Write - Address 0xffc25018 Data 0x00000001 Read and verify...correct! Configuring FPGAPORTRST Configuring STATICCFG_ Write - Address 0xffc2505c Data 0x0000000a Read value without verify 0x00000002 sdram_calculate_memory returns 268435456 sdram set rule start 0, 0 sdram set rule end fff, 0 sdram set rule start 0, 0 sdram set rule end fff, 0 sdram set rule start 0, 0 sdram set rule end fff, 0 sdram set rule start 0, 0 sdram set rule start 0, 0 sdram set rule end ff, 268435456 SDRAM Prot rule, default 3ff Rule 0, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 1, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 2, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 3, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 4, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 5, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 6, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 7, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 8, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 11, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 14, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 Rule 19, rules ... sdram start 0 sdram end fff00000 low prot id 0, hi prot id 0 portmask 0 security 0 result 0 valid 0 SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED sdram_calculate_memory returns 268435456 SDRAM: 256 MiB Setup interrupt controller... IRQ SP at 0x00000000 with size 0x00000400 boot device - 3 ALTERA DWMMC: 0 Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 altera_dwmci_clksel: drvsel 3 smplsel 0 altera_dwmci_clksel: SYSMGR_SDMMCGRP_CTRL_REG = 0x3 Sending CMD0 Sending CMD8 Sending CMD55 Sending CMD41 Sending CMD55 Sending CMD41 Sending CMD2 Sending CMD3 Sending CMD9 Sending CMD13 Sending CMD7 Sending CMD55 Sending CMD51 Sending CMD6 Sending CMD6 Sending CMD55 Sending CMD6 Buswidth = 4, clock: 400000 Buswidth = 4, clock: 5000000 altera_dwmci_clksel: drvsel 3 smplsel 0 altera_dwmci_clksel: SYSMGR_SDMMCGRP_CTRL_REG = 0x3 Sending CMD16 Sending CMD17 boot mode - FAT Sending CMD16 Sending CMD17 Sending CMD16 Sending CMD17 reading u-boot.img Sending CMD16 Sending CMD17 VFAT Support enabled FAT16, fat_sect: 16, fatlength: 256 Rootdir begins at cluster: 0, sector: 528, offset: 42000 Data begins at: 528 Sector size: 512, cluster size: 16 FAT read sect=528, clust_size=16, DIRENTSPERBLOCK=16 Sending CMD16 Sending CMD18 Sending CMD12 Rootvfatname: |zimage| RootMismatch: |zimage|zimage| RootMismatch: |zimage|| Rootvfatname: |u-boot.scr| RootMismatch: |u-boot.scr|u-boot.scr| RootMismatch: |u-boot.scr|| Rootvfatname: |socfpga.dtb| RootMismatch: |socfpga.dtb|socfpga.dtb| RootMismatch: |socfpga.dtb|| Rootvfatname: |system volume information| RootMismatch: |system~1|system volume information| RootMismatch: |system~1|| Rootvfatname: |u-boot.img| RootName: u-boot.img, start: 0x527, size: 0x3f110 Filesize: 258320 bytes 64 bytes gc - clustnum: 1319, startsect: 21632 Sending CMD16 Sending CMD17 Size: 258320, got: 64 spl: payload image: U-Boot 2013.01.01 for socfpga bo▒▒neu|I▒>▒▒▒▒z▒▒.{▒▒▒▒|▒U;▒/&▒_▒▒P▒▒▒▒▒u▒▒▒▒$▒▒▒w▒ng~▒▒W▒   Any ideas where the garbage at the bottom is coming from (It's much longer but i had to short it to fit this message, complete file is attached)? I don't get this without the debug flag set, I'm still digging...

[Altera_Forum]

You can use the debugger help to read back the u-boot.img at SDRAM. 

Then you can compared whether any different with the file content. This can eliminate whether the DDR issue or the u-boot.img itself.

[Altera_Forum]

Thank you very much for your input.  

 I loaded the u-boot.img with the "restore" command to the DDR3 and after lots of experiments, i found out that I had to to adjust the DDR3 Ram settings in Qsys. Strangly, the preconfigured settings from Quartus do not match the datasheet for all parameters.  The board is now up and running.

[Altera_Forum]

Hi all -  

To revive a still-warm topic, I had a question about my first attempts at compiling and using the preloader and u-boot. I see the results here indicate that previous people have gotten further than me on the same board. My board is a 5CSEMA4U23 on the DE0-Nano-SoC kit and I want to be able to do some simple HPS clocking exercises. I have done the following:  1. Loaded the GHRD in Quartus Prime Std. 16.1 and compiled 2. Generated a .rbf binary file from Quartus  3. Used the EDS shell to access bsp-editor and create and subsequently compile both the preloader-mkpimage.bin and u-boot.img files 4. Placed both above files on the SDcard (using alt-boot-disk utility in EDS for the preloader) and added the system .rbf and *.dtb files to the SDcard 5. Tried to boot up  Assume that I have a (previously) working clean kernel of Linux which can be acquired from Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=205&no=941&partno=4) and that initial boot of the Linux fs was successful. Assume also I am interacting via putty serial to my board.  I did these steps following the instructions for the Arrow SoC kit dictated by Kris Chaplin at Altera (https://www.youtube.com/watch?v=vs7pvefsbrm) but I get no data/boot when I run the new SD setup. What is missing? Thanks if you can lend any insight. I did not change any settings on the project from the GHRD, so I imagine the issue is simply something missing or incorrect with the preloader or the u-boot step. Since I can't even get an output from my device over serial maybe it is the preloader.. stumped.

[Altera_Forum]

UPDATE:  

 The issue seemed to be fixed by changing how I generated a .rbf output. Rather than manually creating a compressed *.rbf file from the <File -- Convert Programming> , I switched to auto-generating the *.rbf at compilation-time. After doing that my kernel booted fully. Sorry I don't have better root-cause results to share.

[Altera_Forum]

There is a MSEL setting on board that you need to ensure that is correlate with the type of RBF generated. 

In other word, there is different MSEL setting for compressed and uncompressed RBF. You might want to take a look at FPGA Manager section documentation for more info.