DE1 Flash access problems

Altera_Forum · ‎05-11-2011

Hello forum,

I'm a beginner with NIOS II. I've successfully tested RS232 communication using the uart component in SOPC, however I'm having a hard time with the CFI flash.

This is my configuration:

SOPC block diagram: http://i52.tinypic.com/2znyc77.png

flash configurations: http://i53.tinypic.com/314auyh.png

pin planner: http://i53.tinypic.com/4hqbyg.png

alt_pll is shifting the SDRAM and Flash clock by -6ns. SDRAM works fine though, unlike the flash.

I've tried a different phase shifts for the flash's clock but I fail to nail the right one, maybe. If a phase shift is even needed... I've no idea!

I'm using the following C code (from Nios II Software Developer’s Handbook page 160):

# include <stdio.h># include <string.h># include "sys/alt_flash.h"# define BUF_SIZE 1024
int main() {
    alt_flash_fd* fd;
    int ret_code;
    char source;
    char dest;
    /* Initialize the source buffer to all 0xAA */
    memset(source, 0xAA, BUF_SIZE);
    fd = alt_flash_open_dev("/dev/cfi_flash_0");
    if (fd != NULL) {
        ret_code = alt_write_flash(fd, 0, source, BUF_SIZE);
        if (ret_code == 0) {
            ret_code = alt_read_flash(fd, 0, dest, BUF_SIZE);
            if (ret_code == 0) {
                /*
                 * Success.
                 * At this point, the flash is all 0xAA and we
                 * have read that all back to dest
                 */
            }
        }
        alt_flash_close_dev(fd);
    } else {
        printf("Cannot open flash device\n");
    }
    return 0;
}

It seems that fd == NULL for some reason. I hope you can provide an explanation... :(

I'm sure the problem is somewhere in my HW settings (timing most likely, could be pins too though). I just can't nail the right configuration.