DMA busy

Altera_Forum · ‎05-25-2005

I use a DMA to tranfer 1800 bytes.

The DMA work.

I need to make again the tranfert soon after the first transfer, but it took a long time between the 2 transferL. In fact the DMA is always BUSY.

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_1_BASE, 0x0); // dma transfer disabled

IOWR_ALTERA_AVALON_DMA_STATUS(DMA_1_BASE, 0);

IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_1_BASE, LINE_SIZE);

IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_1_BASE, data_written);

IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_1_BASE, memory_base);

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_1_BASE, 0x2FC);

while((IORD_ALTERA_AVALON_DMA_STATUS(DMA_1_BASE)==(0x2)));

What's wrong? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

Altera_Forum · ‎05-25-2005

Hi,

look at the post "Ethernet and DMA ", maybe you haven't written the correct value in length register...

Altera_Forum · ‎05-25-2005

I have read this topic and it's not the same error because,

LINE_SIZE=1800,

If I select burst mode or not, nothing change.

In sopc builder I put the DMA length register to 11 bits (->2047 bytes).

Altera_Forum · ‎05-25-2005

muffec, it looks like you're trying to read 1800/4 = 450 words sequentially starting at address "data_written", and write each word to the single location at address "memory_base". What is the nature of the slaves at address "data_written" and "memory_base"?

Have you tried simulating this software in ModelSim?

Altera_Forum · ‎05-25-2005

Have you tried using the HAL for doing this? (instead of directly accessing the registers)

Altera_Forum · ‎05-26-2005

--- Quote Start ---

originally posted by kero kero keroppi@May 25 2005, 11:14 AM

muffec, it looks like you're trying to read 1800/4 = 450 words sequentially starting at address "data_written", and write each word to the single location at address "memory_base". what is the nature of the slaves at address "data_written" and "memory_base"?

have you tried simulating this software in modelsim?

--- Quote End ---

thst's rigth i want to read from the SDRAM to the FIFO interface which i took on the forum in "post your own IP". I write, like you say, 450 words.

I'm writting on the fifo in stream mode.

I don't have modelsim.

Altera_Forum · ‎05-26-2005

--- Quote Start ---

originally posted by badomen@May 25 2005, 12:47 PM

have you tried using the hal for doing this? (instead of directly accessing the registers)

--- Quote End ---

yes i try, and nothing better.

Altera_Forum · ‎05-26-2005

I just have seen the number of word really transmitted wasn't goog, there were some lost of data.

I change the control register from 2FC to 28C, it seems to be better. i'll test it.

Thank you for every one who gives me advice.

Altera_Forum · ‎05-26-2005

Ah... I think I know what was happening. Changing from a control register value of 0x2FC to 0x28C turned off the following control register bits:

reen

ween

ien

only the last one, ien (IRQ enable), matters. When your DMA transaction completed, the DMA fired off an interrupt, which was handled by the ISR which the DMA HAL driver init routine installed. That ISR was probably getting in the way of proper function. This all assumes that you aren't using a "freestanding" app (in which you override the initialization code in alt_sys_init.c). Is that true?

The message to take away from all this is, if you want to configure a DMA device with direct register writes (or, presumably, other HAL-driver-equipped component), you should either

1) use a freestanding app, so that HAL driver init for your component can be avoided

2) disable IRQ-generation in your component

3) install your own ISR for your component.

Altera_Forum · ‎06-08-2005

thank you Kero Kero Keroppi for your technical help.

Altera_Forum · ‎06-08-2005

HI, i found your posto on Nios forum, i'm working on same target, a fifo used with DMA.

Can you tell me as you have solved the problem of busy flag ?

second question....

i have configured the dma to work only from dram to fifo, in this case the write address of dmna register, is the sigle location definied into sopc builder ? (i have instantiated the fifo inside the sopc)

regards

Roberto

roberto.buti@virgilio.it

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I had few some problems, because I was waiting to do the transfert on PIO edge and PIO was too long. But the problem on the DMA was the control register, if it hadn't a good value it can made your system do anything or the doing "printf" not writing to screen. I think that you should care a lot of attention to the control register.

I had try to use the Hal fonction library but in thes case of stream mode, it works only if you change the control register with ioctl. Could you give me the part of code which control the DMA?

for your second question, I don't know if the write register is at the base but i tkink yes.

Altera_Forum · ‎06-08-2005

I will try to use it with iocontrl routine, i don't like so much the HAL function for dma. I need one or two days to check the dma, after if is working as i'm expecting i will happy to share the dma use.

roby