DMA memtest.c confusion

[Altera_Forum]

Hi, 

I am using DMA device in my Nios program for DE1 board. The code memtest.c is taken from the example given in Nios IDE. The part of the code is shown below between green arterisk:  ******************************************************# ifdef DMA_NAME  static int MemDMATest(unsigned int memory_base, unsigned int nBytes)  {   int rc;   int ret_code = 0;   int pattern, offset;   alt_dma_txchan txchan;   alt_dma_rxchan rxchan;   void* data_written;   void* data_read;     /* Get a couple buffers for the test */   /* Using the "uncached" version of malloc to avoid cache coherency  issues */   data_written = (void*)alt_uncached_malloc(0x1000);   data_read = (void*)alt_uncached_malloc(0x1000);       /* Fill write buffer with known values */   for (pattern = 1, offset = 0; offset < 0x1000;  pattern++, offset+=4)   {   IOWR_32DIRECT((int)data_written, offset, pattern);   }     /* Create the transmit channel */   if ((txchan = alt_dma_txchan_open("/dev/dma")) == NULL)   {   printf ("Failed to open transmit channel\n");   exit (1);   }     /* Create the receive channel */   if ((rxchan = alt_dma_rxchan_open("/dev/dma")) == NULL)   {   printf ("Failed to open receive channel\n");   exit (1);   }     for(offset = memory_base; offset < (memory_base + nBytes); offset +=  0x1000)   {   /* Use DMA to transfer from write buffer to memory under test */   /* Post the transmit request */   if ((rc = alt_dma_txchan_send (txchan, data_written, 0x1000, NULL,  NULL)) < 0)   {   printf ("Failed to post transmit request, reason = %i\n", rc);   exit (1);   }   *******************************************************  My questions are: In the red for loop: 1) Is it intended that the "offset=+4" ? From what I understand, offset is int and data_written is int pointer. So for this instruction(assume data_written =0x0000),  IOWR_32DIRECT((int)data_written, offset, pattern); would write 'pattern' value into 0x0000 to 0x0003 since is writing 32bit. In the next loop, this instruction will write into 0x000F to 0x0013. This is because data_written+offset=data_written+4=0x0000+0x000F since int 4 translate into 16 byte. So logically thinking,"offset=+1" would be more suitable since it will fill up each memory right?  In the blue for loop: 2) Assuming the memory start from 0x0000 and end at 0x00FF. Does the instruction  if ((rc = alt_dma_txchan_send (txchan, data_written, 0x1000, NULL,   NULL)) < 0)  cause an error since it is reading 0x1000 byte data but the memory is only 0x100 byte ?  Please correct me if I am wrong. Thanks. :)  

[Altera_Forum]

1) the IOWR_*DIRECTmacros always use addresses in a 8-bit space, so with offset at 4 the data will indeed be written at addresses 0x0004 to 0x0007. The code is correct. It would have been different if you had used the [] operator on an int pointer. 

 2) it would still write 0x1000 bytes. Of course only the first 0x0100 bytes would be the ones that you placed there.

[Altera_Forum]

Thanks for the fast reply.:)

[Altera_Forum]

IOWR and IORD use 32 bit word addressing. Any of the macros that have "_8DIRECT", "_16DIRECT", or "32_DIRECT" in the name use byte addressing. 

 I recommend that users use the byte address macros instead of the word address macros for any new software. Likewise on the hardware side any new custom components should always include byte enables for the slave port.

[Altera_Forum]

Hi BadOmen, 

 Thanks for the info. Sorry for being curious. May I know why it is recommended to use byte instead or word? Are there any particular reasons? Please enlighten me. Thanks.:)

[Altera_Forum]

Mainly you should avoid native addressing since it only allows for atomic accesses. The direct macros use specific byte enables based on the access size which is sometimes needed especially during accesses that could be destructive.