DMA

[Altera_Forum]

Hello 

 I have problem with the DMA controller   So, i have 2 memory and with the DMA i would like to transferer data from the first memory in the second. When i declare the DMA i have to paste node read_master and write_master to each memory but i can so how can i do   thanks

[Altera_Forum]

Hi, 

Can u explain better your problem?u are in SOPC builder envoironment, ok?what kind of memory are u using(onchip,external RAM,SDRAM)?what u are not able to do, connect teh read and write master to memory slave ports?

[Altera_Forum]

--- Quote Start ---  originally posted by soin@Jul 13 2005, 05:17 AM hi, can u explain better your problem?u are in sopc builder envoironment, ok?what kind of memory are u using(onchip,external ram,sdram)?what u are not able to do, connect teh read and write master to memory slave ports?  --- Quote End ---   so i have first the dpram (doucble access ram) and the second memory is a SRAM and i would like to read on the DPRAMand transfere the data to the SRAM  thanks

[Altera_Forum]

Hi..  

 It's a very simple,   You just connect DPRAM slave port with DMA Read-Master. It means that DMA Read Master can read data from dpram into DMA FIFO. And connect SRAM slave port with DMA Write-Master. It means that DMA Write Master can write data of DMA FIFO to SRAM.  Regards.

[Altera_Forum]

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif  

Regards, I&#39;m a beginner with DMA and I&#39;m working with Nios I. I&#39;m just doing this little test: reading data from external sram (a block of 64 positions) and writing it in a fifo (my user logic). My fifo is connected with Avalon in this way:  FIFO --> AVALON SIGNAL ---------------------------------- ena --> chipselect } for writing data -->writedata  wrreq --> write rdreq --> read clock --> clk aclr --> reset q --> readdata full --> export } it turns on a led  The only problem is the first address of fifo, because when I read the data (with the traditional method, without DMA) written before with DMA, I get a zero in the first position (0) the first time I run the program. The next times, I get the value that it&#39;s supposed to be in the last position (63).  I&#39;m using nr_dma_copy_range_to_1.  Any help?  Thanks a lot!

[Altera_Forum]

I tested with an Altera FIFO (with show-ahead option activated) and it&#39;s ok. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif  

The thing is that now I need another RAM but it can&#39;t be a FIFO: a control unit gives it the address for writing and RAM gets out the data sequentially if "NiosRead" is high. The problem is reading data from my module again: the first time is just fine, but the second time I run the program the first datum is repeated and the value# 8 is lost. Here is the VHDL code:  LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;  ENTITY ram_idct_out IS  PORT(   NiosCS : IN std_logic;  NiosRead : IN std_logic;  NiosReset : IN std_logic;  clk : IN std_logic;  data_in : IN std_logic_vector (8 DOWNTO 0);  dir_w : IN std_logic_vector (5 DOWNTO 0);  write : IN std_logic;  data_out : OUT std_logic_vector (8 DOWNTO 0)  );  -- Declarations  END ram_idct_out ;   ARCHITECTURE flow OF ram_idct_out IS   -- Architecture declarations  TYPE memory_type is array (63 DOWNTO 0) of   std_logic_vector(8 DOWNTO 0);  SIGNAL memory : memory_type;  SIGNAL rd_addr : integer range 63 DOWNTO 0;  SIGNAL wr_addr: integer range 63 DOWNTO 0;  BEGIN   -----------------------------------------------------------------  process0 : PROCESS (clk, NiosReset)  -----------------------------------------------------------------  BEGIN  -- Asynchronous Reset  IF (NiosReset = &#39;1&#39;) THEN  -- Reset Actions  rd_addr <= 0;  data_out <= (OTHERS => &#39;0&#39;);   ELSIF (clk&#39;EVENT AND clk = &#39;1&#39;) THEN  data_out <= memory(rd_addr);  IF NiosRead = &#39;1&#39; AND NiosCS = &#39;1&#39; THEN  IF rd_addr = 63 THEN  rd_addr <= 0;  ELSE  rd_addr <= rd_addr + 1;  END IF;  END IF;  IF write = &#39;1&#39; THEN  memory(wr_addr) <= data_in;  END IF;   END IF;  END PROCESS process0;   -- Architecture concurrent statements wr_addr <= conv_integer(unsigned(dir_w));  END flow;  Could you please help me? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif Thanks!!!! By the way, I have to add another DMA for reading, I thought that it could work out with only one (for writing and reading).