Dual port memory corruption

[Altera_Forum]

We have system that is using an M9K memory block for IPC between two nios2 cpus. 

 CPU A accesses it as tightly coupled data memory, CPU B via the data port and Avalon bus (no data cache on either cpu). The memory block is set to return OLD_DATA during concurrent read and write.  One of the memory locations contains the 'write pointer' into a ring buffer, this is written by CPU A (actually updated every 125us) and polled by CPU B (along with a couple of other locations) in its idle loop.  On one card the 'OLD_DATA' option doesn't seem to be working properly, CPU B reads 0x00015460 (lots of times), then 0x00015420 (invalid) followed by the valid 0x00015480 (I've added a double read & compare to detect the error).  So it looks as though the read has latched a part-changed value. Does any one know if 'OLD_DATA' actually works correctly, or do we have a more general timing error.

[Altera_Forum]

We've pulled all the enable signal high, now it seems to work. 

I suspect that gating clk (or enable in single clock mode) is done when the nios is stalled on an avalon transfer is a very minor power save.  The TCM reads are done one every cycle - since the value can be fetched before deciding whether the address refers to the specific TCM block. The enable doesn't seem to be gated by the opcode (any 'ldxx' instruction) even though that comparison could be done in the cycle where the register values are read.  The difficulty we have now is actually proving we've really fixed the problem.

[Altera_Forum]

We hadn't fixed it :-( 

 The clk_en is used to hold the address valid for a read that immediately follows an Avalon bus read so that the correct data is read in the cycle after the Avalon bus read actually completes.

[Altera_Forum]

Feeding the clk_en symbol to address_stall_a gives a working system. 

Provided you remember to invert the signal! This is what Qsys does.  This means we have to edit the VHDL generated by sopc every time we regenerate it :-(