Block Type AUTO on-chip memory instantiation, RD ouput transits near rising edges of clk. Adding external mux logic delays the ouput somehow causes some transitions happen exactly at my external logic's sensitive edge (e.x. an ADDER). Data is not stable for external logic processing.
Need help to latch memory read firmly.
Experiment 01 (failed): use a negative edge sensitive register to register memory output. FACT: signal at the register is delayed by half clk cycle but, following logic still behavior the same as the design without register.
Experiment 02 (need multicycle assignment):
use PLL to move the clk of MEM -2ns ahead of other logics. If multicycle = 1 (default), which mean setup relationship is 2ns, paths failed. Since there is a big group of design (referring as huge amout of registers from MEM to following logic) driven by this two clock signals. I don't know how to assignment multicycle to all these register's paths.
And I wonder, the setup violation is calculated according to my timing requirement setting. Circuit may work to mislatch data. Doesn't it mean if I want the design to behavior exactly the same way multicycle setting sets, I have to add additional control scheme to these clocks?
Please help, thanks
