I am trying to contrain the IOs between an EP2C50 and 2 SDRam's each 16Bit wide. The SDRAM Clock is 64MHz with a phase of -67° but i am still not shure wheter this value is correct or not.
The documentation about the SDRAM controller is not clear enough to show from what quartus output i should take the needed values to calculate the phase as it is discribed inside the documenation.
I still wish Altera would have a SDRAM Phase calculator that goves some recommendations with the values of the design from the current timing analyser so i wont need to copy'n'paste the values and have the risk of doing a mistake. (okay phase shift of the pcb is not taken into account)
I am also "playing" (yes playing) with the assignments for each io pin.
has anybody any recommendations about the current strength settings to limit the rise and fall time in order to limit the over and under voltage dips ?
Shall i assign all outputs a fast output register, all inputs a fast input register and for all bidir's fast input output and enable's ?
The goal is that i still want more than a running system, i want to make it as much emc proof as possible by quartus assignments. (Yes signalintegrity is also done on the pcb but every little bit counts)
I am still wondering that i do not find a lot of documents about that at the altera web site.
Regards.
Michael Schmitt
