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EPCS Under Q4.2

Altera_Forum
Honored Contributor II
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Is the documentation correct for the EPCS device controller? 

 

Under Q4.1 the size of the boot loader rom was specified as 256 Words or 1Kbytes, 

The control registers are located immediately after this). 

 

However under Q4.2 I note that the system.h file has a line similar to: 

#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200 

 

Which tends to indicate the registers are now at BASE+512 bytes 

 

Also my UBoot only works when told the registers are at BASE+200 ... 

 

Regards,
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Altera_Forum
Honored Contributor II
399 Views

Yes, the offset has changed. The bootloader was rewritten to take it below 512 bytes so the ROM now fits into one M4K block instead of two. The memory map has been adjusted accordingly.

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Altera_Forum
Honored Contributor II
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With reference to my related thread, have there been any changes that could have affected the boot from epcs option? 

 

I've got a system that worked under Q4.1  

 

with flash at 0x0000_0000 

EPCS at 0x0081_0800 

and  

SDRAM at 0x0100_0000 

 

My reset address is set to 0x0081_0800 

and exception address is 0x0100_0020 

 

and try as I might I can't get the thing to boot code from the EPCS. 

The sof appears to work correctly, the test application (the scrolling leds demo) 

works fine when directly downloaded but I can't program it into the epcs 

 

Even using the supplied NIOS flash programmer (with the system lib set to put all of 

the code elements into SDRAM) I specify the design sof, the executable and that it 

should also program the sof into the epcs but no joy.. 

 

One thing I note is that the ide build process is insisting on using the cfi.srec loader 

rather than the epcs one so how can I ensure it is using the correct one? 

 

 

Any suggestions...?
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Altera_Forum
Honored Contributor II
399 Views

Hello, 

 

There is a bug on EPCS boot in Nios II 1.1, and there is a patch available on altera.com to correct this. The issue will be resolved in the next Nios II release. Perhaps this is the problem? Here is a link to the Nios II errata where the patch is, under the configuration & boot section: 

http://www.altera.com/support/ip/processor...-er.html#config (http://www.altera.com/support/ip/processors/nios2/ips-nios2_devkit1.1-er.html#config)
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Altera_Forum
Honored Contributor II
399 Views

Hurrah! 

 

Yep that got it... who didn&#39;t test their code before releasing it then!? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif  

 

All works lovely now. 

 

thanks Jesse
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Altera_Forum
Honored Contributor II
399 Views

Hi everyone, 

I have nearly the same problems that cybdenw posted. But my design is not using the boot_loader_epcs_bit.s. It uses the boot_loader_cfi.s instead (the reset-address points to flash at 0x0). The software works fine when downloaded directly. But when I use the flash in combination with the bootloader it seems that the program-counter is not set up to the right ram-address after the program-code is transfered to sdram. After system-reset nothing is excecuted, but when I reset the cpu manually after system-reset, the program executes as expected. So, could it be that there is the same error in the cfi-boot-loader, too?
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