EPCS fpga+nios field update

[Altera_Forum]

Hi,  

 I know this has been asked several times, but I can't seem to find an answer that fits my problem so here it goes:    I have a large CIII design with a NIOS including the remote update block.  What I would like to do is to load a new firmware (hw+sw) from an SD card and flash it to the epcs and the restart the system.    So far I have used the an429 example from which i have fittet the parser and programmer to my design. I THINK that the flashing but when the system is restartet my board i dead.    This leaves me with several questions :confused: :   1. Which files from should I used to flash the epcs? right now im using the hw.flash generated from the sof and the epcs0.flash for the nios.    2. How to i now from which address I should boot?    3. am I missing something else? :eek:    thanks!    greetings,   mitch

[Altera_Forum]

There is more than one spot in boot_loader_epcs_bits_sii_siii_ciii.S that has addresses assuming the base address is zero. If you search the file for "sub_epcs_open_address" you should be able to find each spot. For example, there are also direct references to address 48 and 33. I think you also need to add in your offset to the resulting length before the final open. 

 I have never actually tried to modify the boot loader this way so I may have missed a required stop in the above description. Instead, I put my software at a fixed address (not immediately after the .sof) and modified the boot loader to just always use this address.

[Altera_Forum]

Thanks Kevin, but but I'm still not able to run the second software image in my EPCS. 

I change the sources in the boot_loader_files directory and run a make from the EDS command line tool.  I can see that there is a epcs_controller_boot_rom_synth.hex file in my SOPC directory. But I do not understand where this file is coming from. Is this . Is this an ELF converted to HEX when the SOPC generates the NiosII and is coming from the boot_loader_sources/obj directory? 1) I changed the boot_loader_epcs_bits_sii_siii_ciii.S everywhere where I find sub_epcs_open_address:   //First of all I define the base address off the second image (first SOF, ELF is after SOF) movi r_reconfig_image_base, SECOND_IMAGE_ADDRESS // Close & re-open EPCS where we will start extracting the length addi r_flash_ptr, r_reconfig_image_base, 48 // Close & re-open EPCS at byte 33 addi r_flash_ptr, r_reconfig_image_base, 33  2) Then I recompile with the make command in this directory  3) I open the FPGA project of the Second Application and replace the EPCS bootloader in SOPC builder and build again.  4) In Quartus Update Memory Initialisation file and recompile the Quartus project.  5) Then I convert my ELF and SOF files to hex files and create a JIC file and project this  But still my first software image is loaded by the bootloader.  I would expect that my second NiosII does not run at all but I do not expect that it would run the first software image in my EPCS device.   Does any one has a simple bootloader example of Cyclone III with a fixed second software image?

[Altera_Forum]

--- Quote Start ---  3) I open the FPGA project of the Second Application and replace the EPCS bootloader in SOPC builder and build again.  --- Quote End ---  Each time you regenerate your SOPC builder system it will overwrite the hex file with the default boot loader. After each time you regenerate the SOPC builder system you need to copy your compiled boot loader hex file over the default one before compiling the Quartus project.  If you are just trying to replace the boot loader, you can avoid a complete Quartus recompile by just copying your boot loader hex over the old one then do a "Update Memory Initialization File" followed by "Start Assembler".

[Altera_Forum]

--- Quote Start ---  Just to gain some clarity here:  1 - The FPGA will always attempt to load an image starting at address 0 of the EPCS flash unless you've specifically given a different address using the altremote_update core. 2 - The default bootloader for the NIOS when booting from the EPCS will automatically look at the FPGA image, then skip to the end of the file and expect to find the beginning of your software code there.  So here is the question. Are you simply going to overwrite your existing image and software in the EPCS flash or are you planning on keeping a safe image that you'll never overwrite?  You may want to refer to this post: http://www.alteraforum.com/forum/showthread.php?t=5244&referrerid=2226  In any case, the data you want is the raw binary FPGA image data and the binary software data. Here is a script I have given before to produce the binary files (note that in my script I append the software to the FPGA image to create one single file): # Creating .flash file for the FPGA configuration echo Creating firmware flash file ... "$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --compress --input="../altera/top.sof" --output="firmware.flash" # Creating .flash file for software code echo Creating safe and application flash files ... "$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="firmware.flash" --input="../software/top/Release/top.elf" --output="app.flash" # Convert to binary echo Converting flash files to binary ... nios2-elf-objcopy -I srec -O binary firmware.flash firmware.bin nios2-elf-objcopy -I srec -O binary app.flash app.bin # Concatenate echo Concatenating binary files to create final programming file ... cat firmware.bin app.bin > app_image.bin  Jake  --- Quote End ---   i see your configuration.but how do i continue from here?

[Altera_Forum]

Your question is rather vague. What do you have and what are you trying to do? Did you read the answers to your thread here (http://www.alteraforum.com/forum/showthread.php?p=116210)?

[Altera_Forum]

Let me re-phrase my question.I have performed those steps and got the joint bin file.What is my next step?

[Altera_Forum]

The joint bin file needs to be put into the flash. The bootloader included in the EPCS controller will be able to copy the software from flash to RAM when it starts.

[Altera_Forum]

I still did not found an solution... 

I create one JIC file with following images: BLOCK START ADDRESS END ADDRESS hwimage_app1.hex 0x00000000 0x0002FEB3 swimage_app1.hex 0x0002FEB4 0x00038C83 hwimage_app2.hex 0x00090000 0x000BF762 swimage_app2.hex 0x000BF763 0x000C8502  I changed the bootloader of the second hardware image: in boot_loader.h I define the base image address which I give with the JIC creation and use register 21 for this  # define r_reconfig_image_base r21  # define SECOND_IMAGE_ADDRESS 0x90000 in boot_loader.S move this address to r_reconfig_image_base  movi r_reconfig_image_base, SECOND_IMAGE_ADDRESS and in boot_loader_epcs_bits_sii_siii_ciii.S I make use of this register  // 1) Open EPCS-device at flash-offset zero.  mov r_flash_ptr, r_reconfig_image_base   // Close & re-open EPCS where we will start extracting the length  addi r_flash_ptr, r_reconfig_image_base, 48  // Close & re-open EPCS at byte 33  addi r_flash_ptr, r_reconfig_image_base, 33   but after compile, convert to hex, replace in SOPC directoy, update memory initial files and compile in quartus it does not run my NiosII code at all.  Am I missing a simple thing... or do I need to understand the working of the bootloader completely...  Tried to ask Altera for supprt: but their simple answer is: "Altera does not encourage modifying the bootloader". I also have seen the following thread of last week and asked here for help... modifying epcs bootloader (http://www.alteraforum.com/forum/showthread.php?t=28813) I will keep both threads updated if I have an solution...