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EPCS with nios2-flash-programmer

Altera_Forum
Honored Contributor II
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Hi, 

 

I use Quartus 4.1 SP2, NIOSII SP1 

 

my system consists of : EP1C6, CFI FLASH , EPCS1  

or: EP1C6, CFI FLASH , Configuration EPLD) 

(either the Configuration device or the configuration epld is mounted, 

Configuration with EPCS1 needs less power, but hardware image  

update may be dangerous) 

 

in SOPC builder the target board has the following settings for both 

configuration options: 

 

Hardware Image name Module Offset Address 

safe cfi_flash_0 0x00700000 0x00F00000 

user cfi_flash_0 0x00600000 0x00E00000 

epcs_safe asmi 0x00000000 0x00060000 

 

in SOPC Builder ASMI DEVICE is setup as U9, EPCS1, base address 0x0006000 

the application design is setup to generate compressed bitstreams 

(DEVICE&PIN OPTIONS -> PROGRAMMING FILES : 

Active Serial, use configuration device: EPCS1, generate compressed bitstreams) 

 

 

Everything works fine when I use the configuration-epld to boot the  

hardwareimage out of the cfi_flash. 

 

programming the hardwareimage into the epcs1 results in the following: 

 

 

Programming of the CFI Flash works from NIOS IDE FLASH PROGRAMMER and by SHELL 

SCRIPT. 

 

Programming of the EPCS1 with NIOS IDE FLASH PROGRAMMER returns: 

 

make: Entering directory `/cygdrive/i/1DVI02_SOFTWARE/dvi_V01/Debug' 

nios2-flash-programmer --input=ext_flash.flash --sof=`C:/altera/quartus41/sopc_builder/bin/find_sopc_component_dir BOARD_1DVI02_EP1C6`/system/BOARD_1DVI02_EP1C6.sof --device=2 "--cable='USB-Blaster [USB-0]'" --base=0x00800000 

03.11.2004 23:39:09 - (INFO) nios2-flash-programmer: Launching Quartus Programmer to download: 

c:/work/pro/1DVI02_EP1C6/1DVI02_FPGA/BOARD_1DVI02_EP1C6/system/BOARD_1DVI02_EP1C6.sof 

Pre-Reading 150KBytes of data from U1: 

|----.----+----.----| 

********************* (1.547 sec). 

03.11.2004 23:39:14 - (INFO) nios2-flash-programmer: Success. Zero bytes written to U1- 

(because device matched contents of ext_flash.flash) 

03.11.2004 23:39:14 - (INFO) nios2-flash-programmer: Flash programming complete 

make: *** No rule to make target `safe_epcs'. Stop. 

make: Leaving directory `/cygdrive/i/1DVI02_SOFTWARE/dvi_V01/Debug' 

 

 

I tried to program the EPCS1 with a shell script: 

 

 

FPGA_CONF_FILE=../1DVI02_FPGA/standard.sof 

FPGA_FLASH_FILE=standard.flash 

BOARD_CONF_FILE=../1DVI02_FPGA/BOARD_1DVI02_EP1C6/SYSTEM/BOARD_1DVI02_EP1C6.sof 

FP_BASEFLASH=0x00060000 

OFFSET_HW_IMAGE=0x00000000 

JTAG_DEVICE=2 

 

sof2flash --epcs --flash=U9 --input=$FPGA_CONF_FILE --output=$FPGA_FLASH_FILE --offset=$OFFSET_HW_IMAGE 

 

nios2-flash-programmer --epcs --erase --input=$FPGA_FLASH_FILE --sof=$BOARD_CONF_FILE  

--device=$JTAG_DEVICE "--cable='USB-Blaster [USB-0]'" base=FP_BASEFLASH 

 

OUTPUT IS: 

 

04.11.2004 01:49:11 - (FEIN) sof2flash: Starting 

Info: ******************************************************************* 

Info: Running Quartus II Convert_programming_file 

Info: Command: quartus_cpf --no_banner --convert --device=EPCS4 --option=standard.opt ../1DVI02_FPGA/standard.sof standard.pof 

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings 

Info: Processing ended: Thu Nov 04 01:49:12 2004 

Info: Elapsed time: 00:00:00 

Info: ******************************************************************* 

Info: Running Quartus II Convert_programming_file 

Info: Command: quartus_cpf --no_banner --convert standard.pof standard.rpd 

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings 

Info: Processing ended: Thu Nov 04 01:49:13 2004 

Info: Elapsed time: 00:00:00 

04.11.2004 01:49:13 - (FEIN) sof2flash: Done 

04.11.2004 01:49:13 - (INFO) nios2-flash-programmer: Launching Quartus Programmer to download: 

../1DVI02_FPGA/BOARD_1DVI02_EP1C6/SYSTEM/BOARD_1DVI02_EP1C6.sof 

Entirely erasing U9: 

|----.----+----.----| 

********************* (3.063 sec). 

Pre-Reading 93KBytes of data from U9: 

|----.----+----.----| 

********************* (4.719 sec). 

Erasing 3 Sectors: 

|----.----+----.----| 

********************* (2.359 sec). 

Writing 96KBytes : 

|----.----+----.----| 

********************* (1.719 sec). 

Verifying 96KBytes of data: 

|----.----+----.----| 

********************* (3.234 sec). 

04.11.2004 01:49:33 - (INFO) nios2-flash-programmer: Success. Verified 96Kbytes written to U9. 

04.11.2004 01:49:33 - (INFO) nios2-flash-programmer: Flash programming complete 

 

 

It seems that the programmer works ok, but NIOS program does not start, also  

the debugger does not start. 

Both signals NSTATUS and CONF_DONE go high after power up. 

Why does the above first converting program uses "--device=EPCS4" ?
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Altera_Forum
Honored Contributor II
485 Views

 

--- Quote Start ---  

originally posted by fischer@Nov 3 2004, 08:24 PM 

it seems that the programmer works ok, but nios program does not start, also  

the debugger does not start. 

both signals nstatus and conf_done go high after power up. 

why does the above first converting program uses "--device=epcs4" ? 

--- Quote End ---  

 

Did you try selecting the EPCS1 in your Quartus project under Files --> Convert programming files?
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Altera_Forum
Honored Contributor II
484 Views

thanks, 

 

It was not a problem with the flash programmer,  

 

programming of the EPCS1 works with the NiosII Flash programmer  

(only by shell script, not from the IDE) 

and with the quartus programmer by using a JTAG Indirect Configuration File. 

 

There seems to be some timing problem in the startup of my software and the  

timing of other components on the custom board. (the HW configuration from the 

EPCS device is faster than the HW configuration with the configuration epld). I inserted a simple 

usleep(500000) in my software and now the software behaviar is the same as if I load the hw image 

from the configuration epld. 

 

for the problem with the debugger, I made a new debug hardware configuration, 

and now debugging also works. (I still wonder about the fact, that debugging worked, when I loaded the HW image from the configuration EPLD ?)
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