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Error (10170): Verilog HDL syntax error at sha256_pipe.v

Altera_Forum
Honored Contributor II
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Hello all, 

 

I got the following error while trying the Verilog HDL. I'm using Quartus II 13.0. 

 

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "}" 

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "<=", or "=" 

 

 

 

Here is the code: 

 

data15_p1 <= `S1( SS[i-1].data[`IDX(15)] ); 

 

 

 

Can anyone assist please, because I am stumped.  

 

Thanks in advance,
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