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###External 16 bit SRAM ### Help!

Altera_Forum
Honored Contributor II
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Guys and Gurus, 

 

I have a problem here... 

We have a board with 16 bit IDT SRAM and a 8 bit AMD Flash. We are trying to interface it with 32 bit NIOS. We have failed so far. We need help in connecting/specifying this component in the SOPC builder. Anyone has any ideas? 

 

We are stuck and out of ideas... 

 

Thanks and Regards
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Altera_Forum
Honored Contributor II
552 Views

####################################################################### 

 

 

we use ISSI IS61LV25616AL 256k x 16 and AM29LV065 

NIOS [A18..A1] -> SRAM [A17..A0] 

 

Use Interface to userlogic: 

 

Bus Interface Type: Avalon Memory Slave 

 

select add generic list of ports and edit it to 

the following. 

 

PORT NAME | Width | Direction | Shared | Type 

 

address | 18 | input | yes | address  

write_n | 1 | input | yes | write_n  

read_n | 1 | input | yes | read_n  

writedata | 16 | inout | yes | data 

chipselect_n | 1 | input | --- | chipselect_n  

be_n | 2 | input | yes | byteenable_n
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Altera_Forum
Honored Contributor II
552 Views

Had the same problem once. The thing is you cannot just connect 16 bit RAM to a 32 bit bus. You have to shift the address lines accordingly. If you have a 32 bit bus and 32 bit memory then you don't need A0 and A1. Whe adding 16 bit Flash you don't use A0. This is the way used on the development boards. 

 

Now for your design you have to connect your SRAM like the Flash on the development boards and your 8 bit flash must be connected to A0 as well.  

 

What I have found is no matter what I do in the ptf file you cannot fool the system. If will now try to access 16 bit memory in a 32 bit way.  

 

I also assume that you have already made the boards and that you are kind of stuck. So here is my solution. 

 

My simple solution was to write a VHDL patch that shifts the entire requested address bus, now working correctly from a definition, like the plast post, to make the address profile fit the SRAM of Flash. The only problem is that you lose a little speed.  

 

The VHDL code reacts on the Select SRAM signal and translates the address to what it should be. If you cannot get this to work on you side PM me and I will email you the VHDL code. 

 

 

VictorS
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Altera_Forum
Honored Contributor II
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Hi Everyone, 

I figured it out.  

You have to use the Tri-State Bridge. I was trying to interface the SRAM to the Avalon Bridge and it was just not working. I just connected my external glue-logic to the tri-state bus and it works fine. 

 

I also came across a very nice SOPC component for the same. It is posted on  

http://www.fpga.nl/index.html?ipcores.html (http://www.fpga.nl/index.html?ipcores.html)  

Guys, this coomponent is what we shall ever need. Its great. 

 

Thanks and Regards 

Navendujava script:emoticon(':D')
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