FPGA-HPS latency question for the experts

[Altera_Forum]

Hi, 

 i was wandering if you guys can help with the following:  I need to know the latency of the following:  1. from the moment i call some function to transfer 1 byte from bare-metal ARM application to the moment it hits the FPGA fabric...  2. from the moment i write to HPS DDR/ SDRAM using FPGA fabric memory to the moment a bare-metal ARM application see the data....  it will be great if you guys can help!

[Altera_Forum]

This may not satisfy all of your enquiries, but perhaps some of them - take a look: 

https://rocketboards.org/foswiki/view/projects/datamover

[Altera_Forum]

--- Quote Start ---  This may not satisfy all of your enquiries, but perhaps some of them - take a look: https://rocketboards.org/foswiki/view/projects/datamover  --- Quote End ---    thank but i already vised that site /review and the number looks very wired ...  160 ns with 05us jitter?! why the huge jitters? Im sure something was done wrong here on the bare metal part, so im looking to find out if someone had actually try that...   Or  maybe tell me from where the jitter come from?

[Altera_Forum]

I am not sure myself... could it be because Cortex A-series is not a real-time processor? Perhaps others have better insight on this...