FPGA design & user program in EPCS?

[Altera_Forum]

I'd like to put both my FPGA design and my user code into an EPCS device. I've figured out how to put the FPGA design into the EPCS via JIC file but it's not entirely clear to me how the user program goes in there. From reading the bootloader source it appears that the user program gets stored in the EPCS right after the end of the FPGA design. But how do I get it in there? The flash programmer doesn't have a dropdown to select the target for the user program. Can someone answer the questions below: 

 1) Is it enough to use SOPC Builder to set the reset address of the CPU to the EPCS? Will that cause the flash programmer to put my program into the EPCS?  2) Can I create a JIC file that combines the FPGA and user code? Will I still have to set the reset address to the EPCS?  3) Is it still possible to debug the program by loading the SOF file into RAM or do I need a CPU with the reset address in RAM?  Thanks, Andrew

[Altera_Forum]

Hi queisser, 

 > Will that cause the flash programmer to put my program into the EPCS?  I always use the command line for this ... since I can roll it into a make target. Here&#39;s what I do:  1. create the application flash:  $ elf2flash --epcs --base=0x0 --end = 0x7fffffff --flash=<whatever>  --input=<your app elf> --outfile=<your app flash>  2. program the app to the epcs:  $ nios2-flash-programer --epcs --input=<your app flash> --sof=<your pgmr sof>  3. create the flash file for your fpga sof:  $ sof2flash --epcs --input=<fpga sof> --offset=0x0 --output=<fpga flash>  4. program ther fpga image:  $ nios2-flash-programmer --epcs --input=<fpga flash> --sof=<your pgmr sof> --relocate  > Can I create a JIC file that combines the FPGA and user code?  Sorry ... never used JIC.  > Will I still have to set the reset address to the EPCS?  No. The epcs bootloader code just won&#39;t run. So you&#39;ll have to do the bootstrap in your own app.  > Is it still possible to debug the program by loading the SOF file into RAM  Yes. After loading the fpga configuration via jtag, everything will work as normal. If you happen to set your reset address to the epcs bootloader code, it will still grab the application from the epcs.  Regards, --Scott

[Altera_Forum]

Scott, 

 Thanks for the info. I did what you suggest and it worked. The FlashProgrammer tool in the IDE works as well and, of course, does essentially the same thing although the order of burning the SOF and the ELF is reversed. I guess the --relocate takes care of that.  I&#39;m still not clear about the reset address - if I set the reset address to RAM or regular flash, wouldn&#39;t the CPU crash when it jumps there and finds garbage. In other words, wouldn&#39;t loading the user program out of the EPCS necessitate a reset address set to the EPCS?  I&#39;ll try this later but I don&#39;t want to wait for a recompile right now.  Thanks, Andrew

[Altera_Forum]

Hi Andrew, 

 > if I set the reset address to RAM or regular flash, wouldn&#39;t the CPU crash > when it jumps there and finds garbage.  Yes ... if it finds garbage there. I keep a stable boot monitor in the epcs, but I put test code and filesystem images in standard parallel flash. The boot monitor can program the flash much (_MUCH_) faster than the flash programmer (via ethernet).  So for test and debug I just load a sof that has the reset address in the parallel flash via JTAG since it&#39;s much more convenient. If things go belly up, I hit the hw reset and use the image from the epcs -- I&#39;m just plain lazy I suppose ;-)  > wouldn&#39;t loading the user program out of the EPCS necessitate a reset > address set to the EPCS?  Normally, yes. But I may have misunderstood your original question. So, I think we might be talking apples and oranges. You can have a reset address outside of the epcs then jump into the epcs bootloader -- admittedly a hack -- and not necessarily a good practice ;-) -- although it does work fine ... but this is all for test & debug ... not product.  Regards, --Scott