HPS-FPGA data transfer and DMA slow control problem

[Altera_Forum]

Hi all,  

I'm starting a new project with my Arrow SoCKit.  In this project I need to transfer data from the FPGA to the HPS and vice versa very fast ( I hope more than 800 Mb/s).    My question is: which is the best way to do it?   At the moment my idea is:  1) instantiate a ddr3 controller for the HPS  2) enable fpga-toHPS sdram interface  3) instantiate a ddr3 controller for the FPGA (dual port)  4) instantiate a DMA to read from the FPGA memory and write in the HPS memory  5) instantiate a DMA to read from the HPS memory and write in the FPGA memory   using these components the data transfer procedure will be:   FPGA-to-HPS  1) FPGA writes data in the FPGA DDR memory  2) FPGA control DMA for transfer data in the HPS DDR memory  3) HPS reads data from its memory same way for transfer data from the HPS to the FPGA.   Is this the right way?   I made a qsys project (figure). In it I have exported the control_port_slave in the FPGA because I want to control the data transfer with the FPGA.  Now I have these signals:    ctr_address  ctr_chipselect  ctr_readdata  ctr_write_n  ctr_writedata   for each DMA.   Does anyone know the right way to configure the DMA with these signals?    I have tried with this procedure:   1) write the read address register.  2) write the write address register. 3) write the length address register.  4) give the start writing the control register.   Unfortunately this procedure doesn't work. When I write the length register to "00...001111111" in the next rising edge it will become "00...00xxxxxxx"    Can anyone help me?  Thank you

[Altera_Forum]

I am doing the same thing as you are trying to do. Have you made any progress in this.  

 I am actually connecting the DMA to a NIOS, which controls the data transfer from the FPGA to the HPS. But it would be interesting to know how yours is moving along.  also your pictures are too small to read.  cheers