Help: about the socp setting

[Altera_Forum]

Hi, 

 The hardware is Cyclone EP1C6Q and EPCS4. I want to run the Nios II program from on_chip_memory. How to set the reset address, exception address and break address in the SOCP? Also, how about the above address in legacy sdk suport ?  In my design there are on_chip_FIFOs generated from Qautus. How can I write and read the on_chip-FIFOs using Nios II?

[Altera_Forum]

You specify the reset, exception, and break addresses under the CPU settings tab in SOPC builder. If you are starting a new project I recommend sticking to the normal HAL flow (i.e. not the legacy sdk). For your FIFOs you can create a HAL driver or simply do direct accesses via your software. If you do direct access (reading and write from fixed addresses) and you use a Nios core with data cache ('f' core) make sure you bypass the cache when accessing any peripheral. I recommend going to the Altera site and reading the software and hardware handbooks for the Nios II processor since you will find detailed infomation there (including tutorials to help you build up a system).

[Altera_Forum]

for a fifo interface, have a look at mike desimone's ready made solution in fifo interface (http://www.niosforum.com/forum/index.php?act=st&f=15&t=184). 

 Problem is though, that you wont learn so much by using this solution, so reading up on the doc's as suggested by badomen is a good idea.

[Altera_Forum]

Hi, 

 Thanks BadOmen and larsen. But I still have questions.  I want to run the firmware in on_chip_ram. The reset address should be the EPCS4 address. The flash loader program copys the firmware from epcs4 and relocates it to the on_chip_ram. The exception address should in the on_chip_ram address. So maybe the exception handlier will conflit with the firmware. For example, the EPCS4 start address is 0x000000, the on_chip_ram start address is 0x1000000, so the reset address is setted at 0x000000, and the exception address is at 0x100020, is it OK? Why?  I can controll the external RAM or FIFO using Avalon registered bus. How can I create the HAL drivers for on_chip_ram, FIFOs, or user logic? If I use the full flag to interrupt the niosII, how to do?   I have read some Altera documents but finf no answers. What documents shopuld I read?   Thanks!  eRen

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  I want to run the firmware in on_chip_ram. The reset address should be the EPCS4 address. The flash loader program copys the firmware from epcs4 and relocates it to the on_chip_ram. The exception address should in the on_chip_ram address. So maybe the exception handlier will conflit with the firmware. For example, the EPCS4 start address is 0x000000, the on_chip_ram start address is 0x1000000, so the reset address is setted at 0x000000, and the exception address is at 0x100020, is it OK? Why?[/b]  --- Quote End ---    The exception address should be located in the onchip memory range. Did you mean 0x100020 or 0x01000020? (you said onchip ram is located at 0x01000000) Reset should be located at the EPCS controller because it contains a bootloader that you want to run at reset which copies the code compiled for onchip ram (selected in the system library project in the Nios II IDE) into the onchip ram.   <div class='quotetop'>QUOTE </div>  --- Quote Start ---  I can controll the external RAM or FIFO using Avalon registered bus. How can I create the HAL drivers for on_chip_ram, FIFOs, or user logic? If I use the full flag to interrupt the niosII, how to do?[/b]  --- Quote End ---    I&#39;m not going to cover the external RAM since I don&#39;t know what memory you are referring to (you either have it directly mapped, or use a HAL function that handles the protocol between the controller and memory). The full flag can be used as the interrupt signal into SOPC Builder (so add a custom interface to your FIFO with readdata, clk, reset, read_n, irq, etc....) then the interrupt triggers an interrupt service routine to start emptying the FIFO.   <div class='quotetop'>QUOTE </div>  --- Quote Start ---  I have read some Altera documents but finf no answers. What documents shopuld I read?[/b]  --- Quote End ---    http://www.altera.com/literature/hb/nios2/...sw_nii52006.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii52006.pdf) <--- exception handling (for your interrupt) http://www.altera.com/literature/hb/nios2/...sw_nii52010.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii52010.pdf) <--- HAL http://www.altera.com/literature/hb/nios2/...w_nii5v2_02.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii5v2_02.pdf) <--- HAL http://www.altera.com/literature/hb/qts/qt...ts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf) <--- Component Editor  That should get you started.

[Altera_Forum]

Hi BadOmen, 

 Thanks very much for your answer.  The exception address should be located at 0x01000020.  eRen