Hello, I need help for develop a DMA controller to read data from a SDRAM and copy this data into a pheripheral memory. I'm trying to design it in VHDL, but I still can not find the way to initialize a read transfer, to read the SDRAM and copy the data to the peripheral memory.
I need to know if there's a standard state machine process or something like that to correctly initialize a read transfer like the one described above.
I have read the literature from altera, I know the signals that I need in my DMA master port, like waitrequest, master addresss, master readdata, and so on... what I need to know, is something like the sequence in which I have to use these signals, for example something like: "first I wait for waitrequest to be '1', and then output the the master address,etc", or so. I don't really know the sequence to initialize a DMA transaction.
If some of you have an example in VHDL or can give me a kind of "state machine" explanation on how to do it, would be appreciated.
