How does NiosII communicate with other FPGA blocks

Altera_Forum · ‎09-02-2005

Hi,

I am designing a simple CPU+FPGA application. The FPGA has data bus

for setting registers, one at a time. The data bus includes

inputs: TSData[15:0]

Addr [3:0]

TSDataRdy

TSControl

TSControlValid

output: TCdata[15:0]

TCDataRdy

TCControlRdyToAccpet

So, in SOPC, what's the best way to set up the CPU external interface

for talking to FPGA? Should I use PIO or some exsiting memory controller?

Thanks a lot,

Altera_Forum · ‎09-02-2005

Hi,

I think you can use user interface logic.

You can write the proper timing logic between avalon and user interface and add to the SOPC.

Altera_Forum · ‎09-05-2005

Hi,

Maybe a simple question.

How can I make avalon bus available to custom logic module?

Should I choose a component from SOPC builder? Which one?

Thanks!

Altera_Forum · ‎09-06-2005

As I know you need not to add any component called Avalon bus since SOPC Builder by default does all the connections to cpu thru Avalon. You know what all signals you need to connect to Avalon signals. Make an HDL entity where you interface Avalon signals with ur user logic. And add the HDL file of this interface as a new component in SOPC Builder. Read "Avalon Bus Specification" for details on what all signals you require for interfacing with Avalon.

Altera_Forum · ‎09-06-2005

Use component editor (PIO is too simple for most external interfacing). If your interface uses non-Avalon timing add some extra logic to conform to the standard (see the Avalon Bus Spec). If your interface goes off chip and runs at a significantly high speed I recommend re-syncronizing the signals with registers.

Altera_Forum · ‎09-07-2005

Thanks, I found the right document to follow.

Altera_Forum · ‎09-08-2005

Thanks for everyone's replies. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif