How is Nios V's MHARTID csr register assigned a determined value?

[Benitez__Domingo]

Hello,

When multiple instances of the Nios V processor are integrated into a multiprocessor SoC, access to the MHARTID csr register when they execute concurrently is needed to identify the hardware thread.

The Parameters tab of the configuration screen for Nios V in the Platform Designer tool does not allow assigning any value to the MHARTID register.

For Nios II, there is a parameter for manually assigning the CPUID control register value, but for Nios V I do not see a similar parameter.

Then, my question is: how is Nios V's MHARTID csr register assigned a determined value?

Regards,

Domingo.

[JingyangTeh]

Hi

For the MHARTID, this could be set in the platfrom designer under the NiosV IP parameters shown below:

Regards

Jingyang, Teh

[Benitez__Domingo]

Hi,

Thank you for your response.

I am using "Platform Designer 23.1 Build 991 (Quartus Prime Version 23.1std.0 991 11/28/2023 SC Standard Edition)" and these are the options available:

As you can see, there is no parameter for MHARTID.

Which Quartus Prime and Platform Designer versions should I install to allow modifying the MHARTID csr register?

Regards

Domingo

[Benitez__Domingo]

Hi,

I would like to provide additional information. I need to use Quartus Prime Standard Edition because the FPGA device where I am configuring a Nios V/m processor is Cyclone IV. The latest version of Standard Edition for Windows is 23.1.1.

As described in the Nios® V Embedded Processor Design Handbook (Updated for Intel® Quartus® Prime Design Suite: 23.4, date: 2023.12.04), Figure 10 at page 20, the parameter for Nios V/m Microcontroller Intel FPGA IP named "CPU Architecture" has a single option: Enable Pipelining in CPU. The parameter for the MHARTID csr register is not included.

Then I think your previous answer is based on a Quartus Prime 24.x version.

Is that right?

Regards,

Domingo.