How to build up such kind of JTAG_UART application

[Altera_Forum]

I am now using EP2C35 on my board. I have some AD and PLL chips as its peripheral. In order to have a flexible configuration of these chips, I would like to have a NIOS in the FPGA. I wish I can use the NIOS II IDE console to input some command. Then the NIOS can send the control bytes to a RAM in FPGA. Then NIOS will tell configuring Verilog modules for peripheral chips to fetch these control bytes from RAM and send out to the chips. Also I would like to have the NIOS II system as small as possible. During the implementation of the system described above, I've run into some problems: 

 1. How to use small C library? ====================  As a hardware engineer, I am a new comer to the NIOS world. All I can do is to build up a C/C++ application from a template. Say, hello_world_small. I don't wanna use any external SRAM. I've specify the jtag_uart_0 as my stdin and stdout. But if I use the small C library, I will have the error message as follows:  make -s all  Compiling hello_world_small.c... Linking hello_world_small_0.elf... obj/hello_world_small.o(.text+0x34): In function `main': ../hello_world_small.c:78: undefined reference to `scanf' collect2: ld returned 1 exit status make: *** [hello_world_small_0.elf] Error 1 Build completed  I don't know why I cannot use 'scanf'. If I choose not to use small C library, the total elf seems to be huge! around 52K ~ 56K. Surely I don't want this small module take up all the memory in EP2C35.  2. A RAM in the FPGA ==============  I am still not so familiar with Avalon tri-state bridge. Do I have to have one in my system if I want my NIOS to communicate with another RAM (not on-chip memory within NIOS) in the FPGA? Since this RAM is only for control byte storage. It's not necessary to be very large. I still don't know who to implement such kind of structure. I would really appreciate if someone can give me some brief idea.

[Altera_Forum]

--- Quote Start ---  originally posted by zhzhn1980+oct 19 2005, 09:50 am--><div class='quotetop'>quote (zhzhn1980 @ oct 19 2005, 09:50 am)</div>  --- quote start ---  i wish i can use the nios ii ide console to input some command. then the nios can send the control bytes to a ram in fpga. then nios will tell configuring verilog modules for peripheral chips to fetch these control bytes from ram and send out to the chips.[/b]  --- quote end ---   there&#39;s an in-sytem memory contents editor in the altera quartus ii system; you could use that to edit the memory contents directly.  <!--quotebegin-zhzhn1980@Oct 19 2005, 09:50 AM 1. how to use small c library?  --- Quote End ---   The small C library has no interrupt support, IIRC. So there&#39;s no "scanf". You have to read the characters from the UART yourself, then use sscanf(), atol(), strtol(), strtoul(), or something else to deal with them.    --- Quote Start ---  originally posted by zhzhn1980+oct 19 2005, 09:50 am--><div class='quotetop'>quote (zhzhn1980 @ oct 19 2005, 09:50 am)</div>  --- quote start ---  i don&#39;t wanna use any external sram. i&#39;ve specify the jtag_uart_0 as my stdin and stdout.[/b]  --- quote end ---   the stdio library will use quite a bit of on-chip memory.    --- quote start ---  originally posted by zhzhn1980@oct 19 2005, 09:50 am obj/hello_world_small.o(.text+0x34): in function `main&#39;: ../hello_world_small.c:78: undefined reference to `scanf&#39;  --- quote end ---   scanf() requires interrupt support, thus the full c library.    --- quote start ---  originally posted by zhzhn1980@oct 19 2005, 09:50 am if i choose not to use small c library, the total elf seems to be huge! around 52k ~ 56k. surely i don&#39;t want this small module take up all the memory in ep2c35.  --- quote end ---   that memory usage looks about right. there&#39;s a pile of debug symbol tables in the .elf file; this will not be part of the final program image.  to figure out how much memory you&#39;re really using, use the nios2-elf-size command:  nio2-elf-size hello_world_small_0.elf    --- quote start ---  originally posted by zhzhn1980@oct 19 2005, 09:50 am i am still not so familiar with avalon tri-state bridge. do i have to have one in my system if i want my nios to communicate with another ram (not on-chip memory within nios) in the fpga?  --- quote end ---   it&#39;s the easiest way; the alternative is writing your own glue logic... which will wind up looking like the tri-state bridge.  <!--quotebegin-zhzhn1980@Oct 19 2005, 09:50 AM since this ram is only for control byte storage. it&#39;s not necessary to be very large. i still don&#39;t know who to implement such kind of structure. i would really appreciate if someone can give me some brief idea.  --- Quote End ---   That sounds like a job for on-chip RAM.