How to do this?

Altera_Forum · ‎01-09-2006

Hi

I need some help on this:

I designed a NIOS II processor using the SOPC builder. I added a UART (RS-232 serial port) communication component because I am sending data from another PC and the NIOS II processor will forward the data to o/p pins. The UART signals are named RxD and TxD. Now, I have a .vhdl file where I have this line in the entity:

Nios_data_in: in std_logic_vector(8 downto 0);--Nios address bus

So how do I proceed/send the data received on UART RxD to the Nios address bus?

Thanks in advance.

Mick

Altera_Forum · ‎01-10-2006

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originally posted by morfium@Jan 9 2006, 01:10 PM

hi

i need some help on this:

i designed a nios ii processor using the sopc builder. i added a uart (rs-232 serial port) communication component because i am sending data from another pc and the nios ii processor will forward the data to o/p pins. the uart signals are named rxd and txd. now, i have a .vhdl file where i have this line in the entity:

nios_data_in: in std_logic_vector(8 downto 0);--nios address bus

so how do i proceed/send the data received on uart rxd to the nios address bus?

thanks in advance.

mick

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So, let met get this straight. The PC sends data (8 bits wide) to the Rx pin of the NIOS UART component and then you want to output the data to an output port (9 bits wide)

1. Make sure that you are using something like a MAX232 to convert your RS232 signal to 3V3 logic. You can do this by using the 3V3 version or clamp the Rx pin to 3V3. Various ways of doing this. Otherwise your FPGA pin(s) will get roasted by the +-12V

2. You have to declare an output port (component) that is probably 8 bits wide, not 9. This will be fed into your own VHDL block.

3. Write code to interrupt on a RX byte and copy the data received to the PIO component's data.

4. Your VHDL code should look like this for 8 bits:

Nios_data_in: in std_logic_vector(7 downto 0);

for 8 bits. You might have reasons for using the 9th bit.

5. After you have written your code (atleast entity correct) then make a symbol of the VHDL code. You can now insert this symbol on your graphics block diagram and connect it to your NIOS CPU block.

6. Do you have to sync your external code or does it not matter if your get the same value several times in a row? Make sure about that.

And that is about it. Now you just write your VHDL code and recompile to test. You will need to regenerate the symbol if you changed you entity.

Victor Schutte

www.zerksus.com