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How to latch these data?

Altera_Forum
Honored Contributor II
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.......----- ...... ------ 

......|.....|.......|......| 

-----.......------.......------ 

.....X< data >X 

 

--- "...." is used to bring distance control only, other dashes stand for clock signal 

 

Dual port memory output passes through logic arrives at the input port of one synchronous module between two consecutive rising clock edges? 

 

How to deal with this situation? 

 

Thx
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