Honored Contributor II
07-06-2017 09:18 AM
Hello!I'am working with Cyclone V SoC and my custom IP in FPGA writes its data to HPS SDRAM memory. The write transactions are made by simple Avalon MM master port through the F2H bridge. But I need to be sure those writes are fully completed and the data is actually in memory before interrupting Cortex-A9 for further data processing. Can I use avalon bus write response signals for that purpose? At which moment the memory controller acknowledges write transactions? At the moment it receives write transaction in its input FIFO, or at the moment it completely writes actual data to memory? Any advice will be apprrciated.