How to modify this HDL code

Altera_Forum · ‎07-15-2006

module TV_to_VGA ( OSC_27, RESET, VGA_BLANK, VGA_SYNC, VGA_CLOCK, VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B, TD_D, TD_HS, TD_VS ); input OSC_27; input RESET; output VGA_BLANK; output VGA_SYNC; output VGA_CLOCK; output VGA_HS; output VGA_VS; output VGA_R; output VGA_G; output VGA_B; input TD_D; input TD_HS; input TD_VS; wire Y; //4:4:4 Y wire Cb; //4:4:4 Cb wire Cr; //4:4:4 Cr wire mTD_HSx2; itu_r656_decoder U1 ( .CLOCK(OSC_27), //system clock .TD_D(TD_D), //4:2:2 video data stream .TD_HS(TD_HS), //Decoder_hs .TD_VS(TD_VS), //Decoder_vs .Y(Y), //4:4:4 Y .Cb(Cb), //4:4:4 Cb .Cr(Cr), //4:4:4 Cr .HSx2(mTD_HSx2), .blank(VGA_BLANK) ); YCbCr2RGB U2( .Red(VGA_R), .Green(VGA_G), .Blue(VGA_B), .iY(Y), .iCb(Cb), .iCr(Cr), .iRESET(!RESET), .iCLK(OSC_27) ); `include "VGA_Param.h" reg L_COUNTER;//<< reg RL_COUNTER;//<< wire sync_reset=(RL_COUNTER==9)?1:0; reg sync_en;//<< reg delay;//<< reg H_Cont; reg V_Cont; reg oVGA_H_SYNC; reg oVGA_V_SYNC; reg Pre_HS; reg Pre_VS; reg mACT_HS; reg mACT_VS; always@(posedge OSC_27 or negedge sync_en)//<< begin if(!sync_en)//<< begin Pre_HS <= 0; mACT_HS <= 0; H_Cont <= 0; oVGA_H_SYNC <= 0; end else begin Pre_HS <= mTD_HSx2; if({Pre_HS,mTD_HSx2}==2'b10) mACT_HS <= 1; if(mACT_HS) begin // H_Sync Counter if( H_Cont < 852 ) H_Cont <= H_Cont+1; else begin H_Cont <= 0; mACT_HS <= 0; end // H_Sync Generator if( H_Cont < H_SYNC_CYC ) oVGA_H_SYNC <= 0; else oVGA_H_SYNC <= 1; end else begin oVGA_H_SYNC <= 0; H_Cont <= 0; end end end always@(posedge OSC_27 or negedge sync_en)//<< begin if(!sync_en)//<< begin Pre_VS <= 1; mACT_VS <= 0; V_Cont <= 0; oVGA_V_SYNC <= 0; end else begin Pre_VS <= TD_VS; if({Pre_VS,TD_VS}==2'b01) mACT_VS <= 1; if( (H_Cont==1) && mACT_VS) begin // V_Sync Counter if( V_Cont < 524 ) V_Cont <= V_Cont+1; else V_Cont <= 0; // V_Sync Generator if( V_Cont < V_SYNC_CYC ) oVGA_V_SYNC <= 0; else oVGA_V_SYNC <= 1; end end end assign VGA_HS = oVGA_H_SYNC; assign VGA_VS = oVGA_V_SYNC; assign VGA_SYNC = 1'b0; assign VGA_CLOCK = OSC_27; //>>lock detector always @(posedge TD_HS) begin if (TD_VS) L_COUNTER=0; else L_COUNTER=L_COUNTER+1; end always @(posedge TD_VS) begin RL_COUNTER=L_COUNTER;//1714 end always@(negedge sync_reset or posedge TD_VS) begin if (!sync_reset) delay=0; else if (delay < 250) delay=delay+1; end always@(negedge sync_reset or negedge TD_VS) begin if (!sync_reset) sync_en=0; else if (delay < 100) sync_en=0; else sync_en=1; end //<< endmodule

This section of code is for NTSC standard,now I want to change it for PAL standard.

I have made clear the succession of the two standards。NTSC delivers 525 lines of resolution at 60 half-frames per second, and PAL delivers 625 lines at 50 half-frames per second.

Otherwise, the length of odd and even fields for NTSC are all 9,but for PAL,the odd field is 24 and even field 25.

How to modify this code for PAL standard?

Here is the succession for PAL.

http://www.freefpga.com/bbs/upload/200671593647-137.gif

Altera_Forum · ‎07-27-2006

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif ,I can decode the Pal signal based on the de2_tv projection, but this is not the color.

Altera_Forum · ‎08-12-2006

i have the same question! how can convert pal to ntsc using fpga? who have the code? thanks!