How to test SDRAM?

[Altera_Forum]

I would like to know a good way to test SDRAM using NIOS I (not NIOS II). I thought I had a good way; just had a program that wrote various non-overlapping patterns to SDRAM (it ran off on-chip memory, not the SDRAM), and then read them back.. did various shorted/open line checks etc. This passed no problem (and I tested that it would catch errors if I lifted a DQ pin for example)... but then I tried to run code from the SDRAM instead, and nothing would happen. 

 After doing some reading on the forum, the big issue seemed to be phase shifting of the clock. I put a PLL in, and did about a -1.5ns shift (I have 1.2" traces max I believe), and it's now running code, but I'm not confident of the stability. What kind of test can I do while running code on the SDRAM? Two problems that I see are i) You obviously can't overwrite the code space, and ii) There's stack space to consider too. How are these normally dealt with?

[Altera_Forum]

I think the phase shift for stability can only be found by doing exhaustive read/write tests on the SDRAM itself. If you are using an Altera dev kit, then there is a tested default value which should work fine.  

 For future enhancements, if it is available, the PLL can be reconfigured by software, and you can "tune" the PLL phase shift to achieve an optimum setting.   As for the management of program memory space and the heap stack, I do not see a boundary that disallow user from stepping over the very vulnerable memory space. It is up to the user to manage that flexibility.