Is it worth using Tightly Coupled Memory?

[Altera_Forum]

I currently use a NIOS-II/f with instruction and data cache, in a Cyclone. 

 I've looked at the tutorial for using TCM:  http://www.altera.com/literature/tt/tt_nio...ry_tutorial.pdf (http://www.altera.com/literature/tt/tt_nios2_tightly_coupled_memory_tutorial.pdf)  ...and the performance increase over a straight cache seems to be minimal, to the point where the effort required isn't really worth it:  Tightly coupled memory : 18.20 microseconds,  910 clocks. On-chip memory         : 27.48 microseconds, 1374 clocks. On-chip memory (cached): 18.26 microseconds,  913 clocks. SDRAM memory           : 32.80 microseconds, 1640 clocks. SDRAM memory (cached)  : 18.16 microseconds,  908 clocks.  .... or have I misread these results?  What's results have people here experienced, did it make a major difference?

[Altera_Forum]

It depends on what you are doing; tightly coupled memory has the (dis)advantage that it isn't cached. However a large cpu cache rules. It will speed up your application (for example ethernet).

[Altera_Forum]

I think your results show pretty clearly that, in some cases, tightly coupled memory is not worth the hassle. 

 On the other hand, here are some cases in which tightly coupled instruction memory can be very helpful: -It is a way to have some code "cached" that is guaranteed to not contend with other parts of your code, so you can avoid potential "thrashing" of the cache. Since the processor only has direct-map caches, it is easy to have two functions occupying the same cache lines and always bumping each-other out. -If other components or processors are contending for your SDRAM or on-chip mem, and you want guaranteed access to some code.  In your case, it looks like all the important functions fit in the cache and there is no contention with other components. Is that true?