Looping Instructions in Altera Nios

Altera_Forum · ‎08-11-2005

Hai ,

How to write looping constructs like while loop in Altera NIOS?

It is giving some error in while statement .

The code is

always @(posedge clk)

begin

while (count<=10)

begin

@(posedge clk)

k=k+1;

count=count-1;

end

In Leonardo Spec it is working, but it is not working in Altera.

I gave the EDIF generated from Leon spec to Altera, it worked ?

Will it really work well after fusing into FPGA?

Altera_Forum · ‎08-13-2005

You code isn't able to be synthesised.

Altera_Forum · ‎08-15-2005

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originally posted by mohana sundaram.s.v+aug 11 2005, 07:47 am--><div class='quotetop'>quote (mohana sundaram.s.v @ aug 11 2005, 07:47 am)</div>

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in leonardo spec it is working, but it is not working in altera.[/b]

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it's valid simulation code, but not well-designed synthesis code.

<!--quotebegin-mohana sundaram.s.v@Aug 11 2005, 07:47 AM

i gave the edif generated from leon spec to altera, it worked ?

--- Quote End ---

You have to wonder what was actually synthesized. I didn't see the types of "count" and "k" declared in there, so I assume it's manufacturing "int" variables (as opposed to "reg" variables) for you and initializing them to 0. The "count = count - 1" doesn't seem to make sense in that case, though.

--- Quote Start ---

originally posted by mohana sundaram.s.v@Aug 11 2005, 07:47 AM

will it really work well after fusing into fpga?

--- Quote End ---

Only way to be sure would be to build the chip and run it through the Altera simulator.

I wonder what you're trying to create here. It looks like a counter, which would be just:

reg  count;
always @(posedge clk, posedge reset)
  if(reset)
    count <= 0;
  else if(count <= 10)
    count <= count + 1;

In general, you should only have @ events show up once after "always" and never within the begin...end block. Bear in mind that Verilog started life as a simulation language, not a synthesis language, and because of that it looks too much like a sequential programming language like C, which tends to lose the simultaneity of hardware design.

I recommend you obtain the book advanced digital design with the verilog hdl, ISBN 0-13-089161-4.