Loosing chars with avalon_uart

Altera_Forum · ‎06-09-2006

I need to use a serial line under eCos, this one being an avalon UART whose speed is fixed to 115200 bps. Design clock is 25 MHz, giving an error < 0.01 %.

When I read chars without eCos (RTOS = none), things work fine.

However, if I do a similar program with eCos, I am loosing half of bytes !!!

To sumarize, something like (code simplified !) :

cyg_io_lookup("/dev/avalon_uart", &handle);
while (loop)
{
  char data;
  cyg_uint32 len = 1;
  cyg_io_read(handle, &data, &len);
  processChar(data);
}

looses some bytes, while, without RTOS, a code like :

fd = open("/dev/avalon_uart",  O_RDWR | O_NONBLOCK);
while (loop)
{
  char data;
  int n = read(fd, &data, 1);
  if (n > 0)
    processChar(data);
}

works fine.

The test consists in sending less than 10 bytes from a PC, which is less than the capacity of the avalon driver (64 bytes).

Is there something special with this API cyg_io_xxx(), which is new for me ? It looks like read() from UDP socket that discards the unread bytes of a message...

An idea ?

Thanks a lot...

Altera_Forum · ‎06-14-2006

I think the ecos uart driver handles the actual buffer management in a DSR, this will be too slow for 115200. It would work if the altera uart had a 16 byte fifo or something. I had to use my own uart driver with ecos. The rx register is immediately read in the ISR.

Can anyone offer a free uart with fifo, possibly an SOPC-Builder version of the Opencores uart?

Altera_Forum · ‎06-16-2006

I ran into a similar problem, although in my case it appeared that the ISR/DSR could keep up with the 115200 baud rate, but the application rarely ran and so the internal read buffer overflowed. Increasing that size may work if your data is bursty.

I switched to the OpenCore.org 16550 UART with wishbone interface. This uses the standard ecos 16550 drivers. It is fairly easy to make this an Avalon SOPC component. Download the core, read the errata and make the appropriate code changes, and then create a new Component. Load the verilog files and specify the uart_top as the top module. You will then need to assign the wishbone signals to the avalon slave interface. Most are fairly obvious, but wb_stb_i and wb_cyc_i are avalon chipselect and wb_ack_0 is waitrequest_n. If you are connecting to a 32 bit avalon bus there may be gaps between the registers that you need to account for in the driver and the baud rate divisor is dependent on the Avalon Bus speed.

If you have an Altera FAE they can send you an Avalon SOPC module of an older version of the UART core as a starting point.