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I'm trying to project the maximum number of NIOS processors that I can put in various Stratix / Stratix II FPGAs for various instruction and data cache sizes. I'm assuming that the best way to get the most multiple processors and still have performance for the algorithms I'd like to run, would be to a) utilize off-chip SRAM / SDRAM for instruction, rwdata and rodata b) use a large enough instruction cache to contain the main algorithm loop and c) use a large enough data cache to contain the algorithm data.
Now to my question: I've been able to successfully estimate for instance four NIOS II/s (16kB cache) processors (with room to spare) for a Stratix A25 device and even been able to successfully build and run these 4 NIOSs in parallel. I'm not 100% certain yet that 16kB is enough data cache, so I estimated that I could easily get 2 NIOS II/f processors with 16kB instruction and 32kB data cache. My assumption is that the 32kB of cache for each of the data caches could go in each of the 2 72kB of MRAM and the 2 16kB instruction caches could go in the 64kB of M4K memory. Quartus complains that it can't fit this system. When I look at the Ram Summary under the Fitter Resource Section, I see that the huge MRAM memories were used for the 16kB of instruction cache, and then Quartus attempted to use the M4K memory for the larger 32kB cache. Is there anything obvious that I'm overlooking here?? Is there any option to request which type of memory is used by the Fitter for NIOSII instruction vs data cache?? I may not need such a large cache, however I still need to be able to accurately estimate this to the team just in case. Thanks for any thoughts on this! DaleLink Copied
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In the current Nios II 1.1 release, the data cache cannot use M-RAMs due to differences between M-RAMs and M4Ks.
However, I've redesigned the data cache for the next Nios II release due in May so that it can use M-RAMs.- Mark as New
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That is great news. Thanks alot for the response!!
Dale
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