Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12612 Discussions

Missing device tree overlay files from Arria 10 PR reference project

Honored Contributor II

This project appears to be missing the dtso files in the binary distribution: "Arria 10 SoC Hardware Reference Design That Demonstrates Partial Reconfiguration" 



Towards the end of the instructions it says: "The persona dtso files can be converted to dtbo using the command as shown...". Later on it says: "The FPGA overlay DTB (fpga_region.dtso, persona0.dtso, persona1.dtso) as available in the binary linux-socfpga-pr-16.1-a10-bin.tar.gz are hand coded." 



These files are not present in linux-socfpga-pr-16.1-a10-bin.tar.gz. 



The demo on how to perform the partial reconfiguration ( makes reference to these files too. 



I've tried using the sopc2dts tool on the sopcinfo files generated when compiling that project without success. 



Does anyone know how to create fpga_region.dtso, persona0.dtso and persona1.dtso?
0 Kudos
0 Replies