Modelsim simulation error from HLS component.

Nios® V/II Embedded Design Suite (EDS)

Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

Modelsim simulation error from HLS component.

1,078 Views

Hi,

I have abandoned the HLS component top module design in relation to the post I wrote below.

Therefore, I decided to design top module with Verilog and manually instantiate the generated HLS IP.

I created new empty project in Quartus Prime 17.1 standard software and added HLS IP.

Synthesis was run without error. However, a syntax error occurs in the system Verilog sub module

of HLS IP in Modelsim-Intel simulator. I know this simulator version doesn't support mixed language simulation.

Until now, I added -ghdl option to build.bat and could just check with wlf.

Is there any method to simulate in case of me?

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.