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Hi,
I was looking at the NIOS V Processor Reference Manual. I could not find the max instantiations you can implement on a FPGA. I see many designs online of Nios II Multiprocessors. Can I make the assumption that it is the same as the Nios II and you can implement multiple instantiations of NIOS V on the same FPGA, as long as the hardware logic space (alm), memory, etc can support the design.
Lastly, is there any examples online for this?
I see examples like
and
and
https://www.youtube.com/watch?v=O54sJjSjq60
Thanks!
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Hi,
Unfortunately, the official support for Nios V to use Mutex HAL API is not yet supported.
You may implement them at your own accord and we may not be able to support further if you encounter issue.
With this, do you have any further questions?
Again, we apologies giving you this bad news.
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Hi,
Let me check on my side and get back to you.
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Hi,
Unfortunately, the official support for Nios V to use Mutex HAL API is not yet supported.
You may implement them at your own accord and we may not be able to support further if you encounter issue.
With this, do you have any further questions?
Again, we apologies giving you this bad news.
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HI,
Do you have any further questions?
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Hi,
We regret to inform you the bad news on the yet supported feature.
If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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Hi,
GeMRTOS (https://gemrtos.com) supports multiple Nios V/m processors. GeMRTOS is a multiprocessor RTOS that also supports Nios 2/e/f.
The GeMRTOS Platform Designer IP component may be downloaded from https://github.com/G-RTOS/GeMRTOS.
niosv-download issue avoids downloading the .elf file (most of the times) when more than 2 processors are instanciated. This issue was not fixed in Quartus Prime Standard Edition version 22.1 (https://www.intel.com/content/www/us/en/support/programmable/articles/000089679.html).
Regards.
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