Hi folks-
I'm starting the second phase of a multiphase Quartus/NIOS project in which HDL and NIOS C code will run on slightly different hardware platforms. Each phase will use different FPGA devices and, in cases where the FPGA will be the same, the pin assignments may be different. The verilog and C code shared between configurations will be 95% the same. What will differ are the pin assignments, the FPGA device, some of the SOPC Builder components, some of the NIOS source code, and some of the verilog code.
Can anyone point me to something that can enlighten me as to how to set up a Quartus project that will permit me to have selectable configurations under one Quartus project?
Thanks, John Speth
