Hi everyone!
I've designed my own sdram controller in order to archive the highest productivity
for dev. board 1c12 eval. with MT48LC4M32B2-7. The aim is 143 Mhz. The standard sdram
controller runs only at less than 80 Mhz.
For a test mode I chose Count Binary software, system clock 72 MHz and system with
jtag uart and led pio from tutorial. So what I've got so far.
For system with default sdram controller I have no problem even with a byteblasterII
as a programmer, but with the self made sdram controller I've got a next situation:
- Nios IDE downloads program from 0 to f60 included;
- than verify it correctly;
- moreover, start executing and reads first 8 word burst (addr 72-77, 70, 71) and reads
exactly the same data as with default sdram controller;
- and processor dies, there isn't any movement on sdram controller Avalon interface at all.
But system with standard sdram controller at this moment makes a little pause than
reads other words and continues executing successfully.
Furthermore, I've got one more strange thing. Every second (exactly!) attempt to download program is
failed. It writes can't find processor.
I saw by Signal Tap the system is completely stalled with the reset signal at that moment, but
physically the input signal reset_n of nios system is tied to vcc.
Could anyone give me a clue what is wrong?
Thanks in advance.
