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12748 Discussions

NIOS II EPCS bootloader

Altera_Forum
Honored Contributor II
‎06-29-2009 10:33 PM
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I have a Cyclone III and am trying to use EPCS to boot my NIOS II code. I can flash the device with the NIOS Flash Programmer without error but removing the JTAG header and cycling power doesn't appear to start my code. The Verilog code appears to be running. I've configured the NIOS reset vector to point to the EPCS flash controllers address. I've configured the syslib linker section as follows: 

 

Program memory: sdram 

Read-only data memory: onchip_memory 

Read/Write data memory onchip_memory 

Heap memory: onchip_memory 

Stack memory: onchip_memory 

 

 

The syslib RTOS settings is set to "none (single-threaded)" 

 

 

Any debugging tips would be greatly appreciated! 

 

 

Thanks, 

 

Jim 

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Altera_Forum
Honored Contributor II
‎06-29-2009 11:52 PM
501 Views

Look at the final post of this topic (http://alteraforum.com/forum/showthread.php?t=5547) on Altera Forum and try the workaround that it mentions. 

 

Cheers, 

 

- slacker
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Altera_Forum
Honored Contributor II
‎06-30-2009 03:23 PM
501 Views

Thanks Slacker! 

 

I'm trying it now. Its always nice to find these "undocumented features" in software you paid money for! 

 

Jim
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Altera_Forum
Honored Contributor II
‎07-02-2009 08:30 AM
501 Views

Is this fixed in Quartus 9 SP2 ?

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